Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to make an inverter less sensitive to PVT variations?

Status
Not open for further replies.

dirac16

Member level 5
Joined
Jan 20, 2021
Messages
87
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
677
I am trying to use a couple of identical inverters in 0.18um TSMC technology. For the lowest propagation delay I ran a Monte Carlo simulation for a single inverter, where I got ~1ps for the std of the propagation delay, and roughly 13ps for the mean delay. Now if you compute 6*sigma value you get ~6ps variation in the delay, which is not allowed for my application. The best std I wish for is ~200fs. Is there anyway to alleviate PVT variations on the propagation delay?
 

You have the problem that the statistics you
labor under, are probably "cooked" beyond
true process variation and that the real stats
are hidden from the "outside" designer to even
allow you to validate the simulation statistics
which derive from the input MC "stuff".

If you captured the MC low level parameter
variations (e.g. VTP, VTN, U0P, U0N, deltaL{N, P},
TOXN/P (these might vary due to oxide growth
and poly depletion in the process flow as it is,
and so on) then you could regress prop delay
against them and determine the sensitivities.
You might attempt to further dig into -why-
certain params contribute to the scatter (like,
is TOX a problem due to drive strength or is
it about the fanout load, and if it's about fanout
load, do you really need to assert your own
private "max fanout" design guideline?).

You can wish for a 200f/13p=1.5% tolerance
on prop delay but you can expect disappointment
(and plenty of it) if you intend to get that from a
process flow with -3- sigma variations on many
params, on the order of +/-10%. If you can get a
WAT limits & conditions data key then the true
accepted-wafer variation would be made clear
(and you could then litigate in the court of "how
bad do you want it?", whether you should be
held to 6 sigma "put it all on the designer" or
3 sigma "what the fab is really going to squirt out"
design-proof results.
 

If it is a real variation, as opposed to a possible model issue described above, then your only solution would be to calibrate. 200fs is not trivial though.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top