I wanted to know the problem background, which has been clarified now. Standard 74HC4046 has a frequency range
up to 12 MHz, faster 74HC4046A up to 18 MHz. The moderate frequency range makes the design rather easy, although all
basic questions of PLL design, e.g loop filter dimensioning, can be investigated. For 90 MHz, special high frequency components,
e.g. TI TLC2933 would be required. The above mentioned SAA1057 receiver PLL chip is rather special, and in my opinion not well
suited for a general PLL project. It needs e.g. an external VCO oscillator. If you think, that designing a PLL receiver would be
an interesting challenge, you should look at the detail problems involved with it and also ask your instructor, if he's
motivated to support it.