How to make a 2/3 clock freq division?

[mhytr]

For example,generate a 40Mhz clock form a 60Mhz clock.

 

[maksya]

For example,generate a 40Mhz clock form a 60Mhz clock.

Maybe using PLL?

 

[jdhar]

If you fed an inverted clock in, you could generate a 40 Mhz one possibly, but it wouldn't be 50% duty cycle.

 

[eziggurat]

Use phase lock leap. For Xilinx devices, you can use DCM.

 

[sinatra]

1- Divide 60Mhz by 6 and obtain then fa=10MHz.
2- Use a VCO to generate 40Mhz (and cover also other frequencies in the range needed) .
3- Divide the 40MHz from the VCO output by 4 and obtain fb=10MHz.
4- Compare the phases of fa and fb using a phase-frequency detector (PFD).
5- Use the output of the PFD to correct the phase/frequency of the VCO.
6- If your VCO has lower phase noise than your 60MHz reference signal a low pass filter in the control loop could also help to reduce jitter at the 40MHz output coming from the 60MHz reference.
7- The output of the VCO will be the required signal (2/3 of the 60MHz reference signal).

Hope it helps.
S.

PS: The division by 6 can be performed by a programmable divider by 3 followed by a t-flip-flop (divider by 2) to provide a 50% duty cycle (10MHz).

 

[xysafety]

For FPGA, the DCM is enough.
but for ASIC, taking the area and cost in consideration
DLL or PLL is optional.
But I prefer the DLL due to the low frequency.

 

[Matrix_YL]

1- Divide 60Mhz by 6 and obtain then fa=10MHz.
2- Use a VCO to generate 40Mhz (and cover also other frequencies in the range needed) .
3- Divide the 40MHz from the VCO output by 4 and obtain fb=10MHz.
4- Compare the phases of fa and fb using a phase-frequency detector (PFD).
5- Use the output of the PFD to correct the phase/frequency of the VCO.
6- If your VCO has lower phase noise than your 60MHz reference signal a low pass filter in the control loop could also help to reduce jitter at the 40MHz output coming from the 60MHz reference.
7- The output of the VCO will be the required signal (2/3 of the 60MHz reference signal).

Hope it helps.
S.

PS: The division by 6 can be performed by a programmable divider by 3 followed by a t-flip-flop (divider by 2) to provide a 50% duty cycle (10MHz).

Can anyone give an example?

 

[nand_gates]

Checkout This code.....
Hope this helps!

module div_2by3(/*AUTOARG*/
   // Outputs
   clk_2by3, 
   // Inputs
   clk, reset_n
   );
   input clk, reset_n;
   output      clk_2by3;
   reg   [1:0]  clk_by3_pos, clk_by3_neg ;
   assign      clk_2by3 = (~clk_by3_neg[0] & clk_by3_pos[0]) | (clk_by3_neg[1] & clk_by3_pos[1]);
   
   always @(posedge clk or negedge reset_n)
     if (!reset_n)
       clk_by3_pos <= 0;
     else
       if (clk_by3_pos == 2)
         clk_by3_pos <= 0;
       else
         clk_by3_pos <= clk_by3_pos + 1;

   always @(negedge clk or negedge reset_n)
     if (!reset_n)
       clk_by3_neg <= 0;
     else
       if (clk_by3_neg == 2)
         clk_by3_neg <= 0;  
       else
         clk_by3_neg <= clk_by3_neg + 1;
   
endmodule // div_2by3

 

[jdhar]

for some reason, I assumed he didn't have a PLL

 

[rogk]

a general method is to use is a DDS clock synthesizer.... it really depends how accurate you want your clock to be (over the long term) - which you can essentially set by the size of the register. obviously the duty cycle is going to wobble around in the short term. anyway - all it is really is a free-running counter where the MSB toggles as your resultant clock.

`define DDS_ACCUM_SIZE 8

/* tuning word = ((Fout / Fck) * ACM)
where: Fout = required output frequency
Fck = DDS source clock (60MHz)
ACM = Accumulator states (2powN)
*/
// ((40/60)*256)
`define WSTEP 8'haa

module DDS (Clk, DDS_ClkIn, notRESET, DDS_ClkOut);
input Clk; // Main core clock
input DDS_ClkIn; // Fast DDS input clock
output DDS_ClkOut;
reg DDS_ClkOut;
// internal registers
reg [`DDS_ACCUM_SIZE-1:0] A; // accumulator
// phase accumulator...
always @(posedge DDS_ClkIn or negedge notRESET) begin
if(!notRESET) A <= `DDS_ACCUM_SIZE'b0;
else A <= (A + `WSTEP);
end
// DDS clock output is MSB of accumulator
always @(posedge DDS_ClkIn or negedge notRESET) begin
if(!notRESET) DDS_ClkOut <= 0;
else DDS_ClkOut <= A[`DDS_ACCUM_SIZE-1];
end
endmodule // DDS


ps. can i ask someone a question? how do I post this without all the indentation getting chewed off? (apologies for this simpleton query!) ;o)