[SOLVED] How to make 3D RAM in VHDL

153rd said:

Hey guys,

I have a question regarding RAM.

I want to show something on a VGA monitor( in 320 x 240).

I have to make a video driver, and I use 3 bits for color( 1 red, 1 green, 1 blue).
The video driver reads data from the RAM memory.

What I can do, is make an array of (320 x 3) x (240) ==> 960 x 240.

But this is a bit cumbersome if I'd want to change the image, I'd have to change each bit manually.

The only way I know to make RAM is : type RAMTYPE is array( x downto 0) of std_logic_vector(y downto 0);
I tried to use array(x downto 0) of array(y downto 0) of std_logic_vector(z downto 0),
wich (as expected ) didnt work.

Is there a way to make a 3D array in VHDL?

Click to expand...

shaiko said:

Remember:
3D RAM is unsynthesizable

Click to expand...

153rd said:

Kevin, thank you very much for your help. But shaiko, is there a workaround to make 3d ram then?

Click to expand...

153rd said:

thanks a lot guys!

Click to expand...

shaiko said:

Remember:
3D RAM is unsynthesizable

Click to expand...

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_ram is
  
  port (
    
    ------------------------------------------------------------
    --Clock and reset
    ------------------------------------------------------------
    clk                       : in  std_logic;
    reset                     : in  std_logic;
    
    
    addr_in                   : in  integer range 0 to 255;
    d_in                      : in  std_logic_vector(31 downto 0);
    w_en                      : in  std_logic;
    
    addr_out                  : in  integer range 0 to 1023;
    d_out                     : out std_logic_vector(7 downto 0)
    
  );
end entity;
  
architecture rtl of test_ram is
  
  type bytes_t is array(0 to 3) of std_logic_vector(7 downto 0);
  type ram_3d_t is array(0 to 255) of bytes_t;
  signal ram_3d     : ram_3d_t;
begin
  
  
  process(clk)
  begin
    if rising_edge(clk) then
      
      
      if w_en = '1' then
        ram_3d( addr_in ) <= ( d_in(31 downto 24),d_in(23 downto 16), d_in(15 downto 8), d_in(7 downto 0) );
      end if;
      
      d_out <= ram_3d( addr_out/4 )(addr_out rem 4);
    end if;
  end process;
  
end rtl;