how to link 32bit ALU program output as a input to the 32 LFSR to generate pattern

[Charan Rathod]

how to link 32bit ALU program output as a input to the 32 LFSR to generate pattern
these are code;

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Code Verilog - [expand]
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:12:55 08/20/2014 
// Design Name: 
// Module Name:    again 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    00:20:56 08/19/2014 
// Design Name: 
// Module Name:    gg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module alu(
    output [31:0] out,
    output c_out,
    input [3:0] code,
    input [31:0] a,b, 
    input cin
 );
     
 parameter andb=0;
 parameter nandb=1;
 parameter orb=2;
 parameter norb=3;
 parameter xorb=4;
 parameter xnorb=5;
 parameter nota=6;
 parameter lsft=7;
 parameter rsft=8;
 parameter add=9; 
 parameter sub=10;
 parameter mul=11;
 parameter div=12;
 parameter mod=13;
 parameter fadd=14;
 reg [31:0] out;
 reg c_out;
 always @ (code,a,b,cin)
          case(code)
                   andb  : out = a & b;
                   nandb : out = ~(a & b);
                   orb   : out = a | b;
                   norb  : out = ~(a | b);
                   xorb  : out = a ^ b;
                    xnorb : out = ~(a ^ b);
                   nota  : out = ~a;
                   lsft  : out = a<<b;
                   rsft  : out = a>>b;
                  
                   add  : out = a + b;
                   sub  : out = a - b;
                   mul  : out = a * b;
                   div  : out = a / b;
                   mod  : out = a % b;
                   fadd : {c_out,out} = a+b+cin;
            default:{c_out,out} = 5'bxxxxx;
   endcase
    endmodule 
    
     module MAIN(Lclk,Lrst,Lfsr,Lcnt,Aout,Ac_out, Acode,Aa,Ab,Acin,Aout3);
     input Lclk;
     input Lrst;
     output reg [31:0] Lfsr;
    output reg [31:0] Lcnt;
      input [3:0] Acode;
    input [31:0] Aa,Ab; 
    input Acin;
     output [31:0] Aout;
    output Ac_out;
     input[31:0]Aout3;
     alu B22(Aout,Ac_out,Acode,Aa,Ab);
     assign Aout3=Aout;
    //lsfr A2(Aout,Lclk,Lrst,Lfsr,Lcnt);
    lsfr A2(.out1(Aout3),.clk(clk),.rst(rst));
    
     endmodule 
 
     
module lsfr (out1,clk,rst,lsfr,cnt);
input [31:0] out1; 
input clk;
input rst;
output reg [31:0] lsfr;
output reg [31:0] cnt;
always @ (!rst)
 
begin
lsfr <=out1;
cnt <= 'd1; 
 
end  
always @ (posedge clk)
 
begin
if ( lsfr ==32'b11111111111111111111111111111111)
cnt <= 'd1; 
else
cnt <= cnt + 1'b1;
 
end 
always @ ( posedge clk)
begin
lsfr[0] <= lsfr [1]^lsfr[0]; 
lsfr[1] <= lsfr[2];
lsfr[2] <= lsfr[3];
lsfr[3] <= lsfr[4];;
lsfr[4] <= lsfr[5];
lsfr[5] <= lsfr[6];
lsfr[6] <= lsfr[7];
lsfr[7] <= lsfr[8];
lsfr[8] <= lsfr[9];
lsfr[9] <= lsfr[10];
lsfr[10] <= lsfr[11];
lsfr[11] <= lsfr[12];
lsfr[12] <= lsfr[13];
lsfr[13] <= lsfr[14];
lsfr[14] <= lsfr[15];
lsfr[15] <= lsfr[16];
lsfr[16] <= lsfr[17];
lsfr[17] <= lsfr[18];
lsfr[18] <= lsfr[19];
lsfr[19] <= lsfr[20]; 
lsfr[20] <= lsfr[21]^lsfr[1];
lsfr[21] <= lsfr[22]; 
lsfr[22] <= lsfr[23];
lsfr[23] <= lsfr[24];
lsfr[24] <= lsfr[25];
lsfr[25] <= lsfr[26];
lsfr[26] <= lsfr[27];
lsfr[27] <= lsfr[28];
lsfr[28] <= lsfr[29]; 
lsfr[30] <= lsfr[31]^lsfr[21];
lsfr[31] <= lsfr[0];
end
endmodule

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You are assigning lsfr from 2 different always blocks, that results in a multi-driver problem in the code and in synthesis. (why is it called lsfr and not lfsr?)

I think you should read about LFSR on wiki: https://en.wikipedia.org/wiki/Linear_feedback_shift_register your LFSR structure is incorrect. You are feeding bits around instead of XORing the output bit with the tap position, look a the Galois LFSR description.

It appears you don't know how to use make an asynchronous reset, or that the lsfr is easier to code as a concatenation.

You should code your lsfr like so:

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Code Verilog - [expand]
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always @ (posedge clk, negedge rst) begin
  if (!rst) begin
    lsfr <= out1;
  end else begin
    // taps at 32,22,2,1, note: taps at 32,30,26,25 should also work
    lsfr <= {lsfr[0],lsfr[31:23],lsfr[22]^lsfr[0],lsfr[21:3],lsfr[2]^lsfr[0],lsfr[1]};
  end
end

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If my positions are off by one forgive me I usually draw them first and then code accordingly, but in this case I didn't do that.

You should also fix the cnt and include the rst in the clocked always block.


Regards