Re: First step to FPGA
Going through doccumentations may not be the best approach if you don't know the basic structures of an FPGA.
To begin, it depend on if you have previous knowledge of any programmable logic, like simple PLD (PAL, GAL, ...). This is not required, but will at least give you an idea of how PLD, CPLD, and FPGA work. At a minimum, you need to have knowledge of logic gates (and/or/xor/...), and flip-flops. I mean, how they work...
Basically, an FPGA is composed of only a few relatively simple modules. Those modules are then interconnected togetter to form a more complex function.
One of the module is a logic cell. A logic cell is contain a LUT (look-up table) and a register (a single flip-flop). It also contains some gates, so that multiple LUT output can be combined together.
A LUT, a look-up table, is the equivalent of a PLD logic array. However, in a PLD, where you define connections between OR and AND gates, a LUT is simply a ROM-like structure (at runtime). It usually have 4 inputs, and give one output depending on the inputs. So, you could encode something like (A AND B) OR (/C AND D). The LUT is a simple table that for every A, B, C and D inputs, it output the corresponding output.
The flip-flop can be used as a single register element, controled by a CLK signal. It also have set and reset signals (synchronous and asynchronous).
The logic cell also have some specialized lines, like 'carry' lines. So, multiple cells can be joint together to create shift-register or added.
An FPGA usually contain hundreds to thousands of logic cells. Each of those cells are connected together via multiple lines. When you create a design, the program automatically connect some of those lines together to form a path between the different logic cells, depending on your design.
Another part of the FPGA is the IO Block. Each pins on your FPGA have one IOB. The IOB interface between the FPGA and the external world. For example, it can be programmed to generate TTL signals, CMOS signals, PCI signals, ... The IOB also have some flip-flop, so that the output from a flip-flip to the external world take less time (in the order of a few nanoseconds). However, IOB doesn't contain any logic functions, as they are in logic cells.
Memory structures can be constructed from logic cells, but if you need a moderate amount of memory (more than 256 bytes), this will consume a lot of logic cells. This is why many FPGA contain what they call 'distributed RAM'. Some logic cells can be 're-programmed' as simple RAM structure (this is really FPGA-dependent). And some FPGA have dedicated RAM blocks (in the order of 4K to 16K bits, configurable for example as 512x8 bits, or 512 bytes). For higher memore requirement (like 256K or RAM) you need to use external RAM. FPGA isn't a RAM device, and doesn't provice much RAM. This is to save FPGA chip space for logic design. However, FPGA RAM is good for example for implementing level-1 cache.
To desing an FPGA project, you need a specialized program set. The program take some input files and generate output for the FPGA. Think of those input files as source code (analog to a 'cpp' file for C++ compilers). However, 'cpp' and other software-targetted language can't handle hardware designs. This is because in software, every instructions are ment to be followed using a sequential structure. In hardware, every modules work in parallel. So, a specialized language is needed, a language that can describe the hardware, an hardware description language (HDL). Two of the most popular languages are VHDL and VerilogHDL. They are as different as in Pascal and C. They both achieve the same result, they both have strength and weakness. If you know one, you have to re-learn if you wish to use the other, but the basic structure share some similarity.
VHDL is very popular, and is one of the first language written. However, it have been written long ago, and therefore, have encounteres several modifications to meet the industry requirements (FPGA). Verilog on the other hand is newer. It have less support, but is, in my opinion, easier to learn. If you have knowledge of programing language, like C, it will be easier to learn. Verilog is growing very fast in popularity, and is supported by most FPGA software programs. VHDL is much more textual (needing a lot of text to tell only a few things), however, it have more support (i.e., you'll find more source codes and examples written in VHDL).
So, what you need is to learn HDL, a set of tools to 'compile' the HDL to binary file (for FPGA), an FPGA
and a way to program the binary file to the FPGA. Actually, the binary file is sent to a configuration memory (a flash), that is 'loaded' by the FPGA when it start. Optionally, you can manually send the program directly to the FPGA, but this is not suitable for stand-alone operations.
Many boards come with an FPGA configurator memory, but watch to make sure it have, unless you wish your board to be constantly connected to your PC, and hitting the 'download' button each time the FPGA is re-powered.
From here, you can look at FPGA basic tutorials, or if you wish, you can have a look at the different blocks of an FPGA described above (this is described in the manufacturer documents).