I think you are not selected the flags (that you wants) during the FIFO generation using the Xilinx Logic Core generator. The things are there in the 3rd page of the Xilinx Logic Core generator, when you generating the FIFO... also the the read data count and the write data count are at the 5th page...
Yes, you must tick the flag names if you want to be available. Also I would suggest not to enable these flags if you plan not to use. You can avoid un-necessary nets...