Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to instantiate an ADC module in verilog-AMS?

Status
Not open for further replies.

ruwan2

Member level 5
Joined
Nov 29, 2011
Messages
90
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
2,141
Hi,
I learn verilog-AMS with SMASH. After I follow a simple example project pll, I create an ADC project (copy this module from the LRM). In the .pat file I have the substantiation:


.lib "source.vams"

adc1 0 src1 out adc NLO=VSS NHI=VCC
xvsrc1 src1 0 sinVarFreq freq=5.5e1 coeff=4.0


but it always has the error message:


ERROR: ADC1: cannot set value 'src1' for parameter 'NLO'
ERROR: ADC1: cannot be instantiated (none model name 'adc' definition is found)

The definition of NLO is:


Parameters description
NLO
Name of net for voltage representing logic 0.



I cannot figure out how to make this adc module work.


Here is the adc module file:

module adc(in, clk, out);
parameter bits = 8, fullscale = 1.0, dly = 0, ttime = 10n;
input in, clk;
output [0:bits-1] out;
electrical in, clk;
electrical [0:bits-1] out;
real sample, thresh;
integer result[0:bits-1];
genvar i;
analog begin
@(cross(V(clk)-2.5, +1)) begin
sample = V(in);
thresh = fullscale/2.0;
for (i = bits - 1; i >= 0; i = i - 1) begin
if (sample > thresh) begin
result = 1.0;
sample = sample - thresh;
end
else begin
result = 0.0;
end
sample = 2.0*sample;
end
end
for (i = 0; i < bits; i = i + 1) begin
V(out) <+ transition(result, dly, ttime);
end
end
endmodule



Here I modify a sine wave generator as a clk signal output:


`include "disciplines.vams"
`include "constants.vams"

module sinVarFreq(p, n);

inout p, n;
electrical p, n;

parameter real freq = 1.0e2;
parameter real coeff = 1.0;
real tempr;

analog begin
V(p,n) <+ (sin(`M_TWO_PI * freq * (0 + 1.0) * $abstime) > 0) ? 1 : -1;
end
endmodule



Thanks,
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top