I am trying to infer 128 bit register in spartan-3 FPGA. when i implement the design i get error during the mapping stage " The design is too large for the given device and package."
it is mapping the flipflops to iobs and the package xc3s200 doesnt have enough iobs .
But if the output of the 128-bit register is part of the interface (port in VHDL), synthesis will work, but implementation may try to move the register to the IOBs.
It doesn't really matter if the FFs are in CLBs or IOBs. If all 128 output bits are being connected to IO pins, and your package is too small, you get the "design is too large" error message.
It doesn't really matter if the FFs are in CLBs or IOBs. If all 128 output bits are being connected to IO pins, and your package is too small, you get the "design is too large" error message.
If u r having more number of outputs than what are available, error message will come.
Anyways, IOB fitting can be changed by (in XILINX ISE):
1. Right Click on MAP in Implement Design (in Process Window)
2. Select Properties
3. Turn off Pack I/O Registers/Latches into IOBs option.