How to increment a value every n times

[LatticeSemiconductor]

Hi, i am trying to increment a value ^^
What i want to do is reducing the number how often it increments linearly. For example, in the first round, it increments every clock cycle, in the second round increments three times every 4 clock cycles, then once every 2nd, then once every 4th clock cycle. The problem is, the steps i want to use is 255, like so:

R1 : increments 255 clock cycles every 255 clock cycles
R2 : increments 254 clock cycles every 255 clock cycles
.
.
.
R51 : increments 4 clock cycles every 5 clock cycles
...
R85 : increments 2 clock cycles every 3 clock cycles
...
R170 : increments 1 clock cycles every 3 clock cycles
...
R254 : increments 1 clock cycle every 255 clock cycles
R255 : increments 0 clock cycles


The solution i came up with was using a shift register of 255 bits to implement this (as a flag to increment).

I wonder if there is a smarter way to do such ???

 

[ads-ee]

Hi, i am trying to increment a value ^^
What i want to do is reducing the number how often it increments linearly. For example, in the first round, it increments every clock cycle, in the second round increments three times every 4 clock cycles, then once every 2nd, then once every 4th clock cycle. The problem is, the steps i want to use is 255, like so:

This is a poor explanation of your requirements.

R1 : increments 255 clock cycles every 255 clock cycles
R2 : increments 254 clock cycles every 255 clock cycles
.
.
.
R51 : increments 4 clock cycles every 5 clock cycles
...
R85 : increments 2 clock cycles every 3 clock cycles
...
R170 : increments 1 clock cycles every 3 clock cycles
...
R254 : increments 1 clock cycle every 255 clock cycles
R255 : increments 0 clock cycles

Even worse, this is an exceptionally bad example of what you are trying to implement.

So does R51 : increments 4 clock cycles every 5 clock cycles mean that the number of clock cycles for the interval changes to 5 until it reaches Round 85, where it changes to 3? As you can't seem to explain to others what you are trying to do, does this mean you don't understand exactly what you are supposed to implement?

 

[KlausST]

Hi,

look for NCO, DCO, DDS.

Maybe this is what you need.

****

To your problem:

btw: your explanation example is not linear:
I´d like to change a bit to make it linear:

D0 increments never
D1 increments 1 clock every 256 clock cycles
D2 increments 2 clock every 256 clock cycles
D3 increments 3 clock every 256 clock cycles
...
D255 increments 255 clock every 256 clock cycles
D256 increments 256 clock every 256 clock cycles (every clock)

here D is about 255 - R (your "R")

how to do:

imagine a 16 bit unsigned integer variable called "cnt"
and a 16 bit unsigned integer variable called "D"

every clock add "D" to "cnt": cnt = cnt + D
now look at the upper 8 bits of "cnt" and you have the result

Good luck

Klaus

 

[D.A.(Tony)Stewart]

Rather than guess on a implementation solution without defining the real task, Define the real purpose, then what you tried and then ask for suggestions.

i.e is this to synthesize a clock with a binary controlled range of sweep frequencies using 1 to 256 divide ratios then sweep frequencies with a fixed pulse width then sweep duty cycles while sweeping frequency then repeat?

What is the outcome result in time or frequency domain or is this a channel excitation sweep generator?

While you are at how about a list of 256 random consecutive integer frequencies and phases, then shuffle all the values and deal them out sequentally for one cycle, reshuffle and repeat? (rhetorical question)

My point is what is the point of the exercise? This is more important than the implementations suggested in defining a question.

 

[LatticeSemiconductor]

Sorry about that, i'll try to explain what i intend to do:

---

Code VHDL - [expand]
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process( clock, reset )
  begin
    if (RESET = '1') then                                      -- start all zero
      -- initiate data
    elsif(CLK_SYS'event and CLK_SYS = '1') then
      if (enable = '0') then                                    -- set all zero
        -- initiate data
      elsif (...) then                                            -- when enable
        if (...) then                                              -- just before active and after that    
          -- initialize values
        else                                                        -- when active, do something
          if ... then                                                  -- when maximum value has reached  
            -- initiate data
          elsif ... then                                              -- otherwise, when flag set
            -- increment data with constant value   
          end if ;
        end if;
      end if;
    end if;
  end process;

---

Explanation to the code:
data increments from 0 to maximum value, repeatedly
data increments by a value stored in register (remains constant)

On this part:

---

Code VHDL - [expand]
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elsif ... then                                              -- otherwise, when flag set
-- increment data with constant value   
end if ;

---

i would like to set a flag to increment data, but the number of times it increments decreases from 255 to 0

               _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   
   clock     _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |
              :_______________:_______________:_______________:_______________:_______________:_
   lap        X_______0_______X_______1_______X_______2_______X_______3_______X_______4_______X_
              :_______________:___________    :___     ___    :___            :               :                            
   inc_flag  _|     4x1       :    3x1    |___| 2 |_x_| 1 |___|   |__1x1______:_____0x1_______:
                              :               :               :               :               :

The timing diagram shows what it would look like if it would decrease from 4 to 0 (just to simplify)

Thanks for your answers until now. I agree with you, it was a poor explanation and - its not linear as well
Anyway, i'm tired now so maybe i missed something here. i won't have access to the internet for the next few days or so so i wont post anything soon.
When i wrote "round" in my 1st post, i meant lap. i made a mistake on translation.

 

[ads-ee]

I still don't think you've given an adequate explanation of the problem. Specifically when the inc_flag is broken evenly into the lap. Your original example for the 255 clock duration lap shows the following discrepancies from a single high-low pulse.
L51 : 4-1 x51
L85 : 2-1 x85
L170 : 1-2 x85
where
L# is the lap number
High-Low xIterations => (High+Low)*Iterations = 255

This neglects the multitude of other possible cases of evenly divisible intervals that result in sometime multiple possible pulse sequences for one lap. e.g.

Each loop is 255 clock cycles long:
Loop# : High_cnt-Low_cnt <xREPEAT> 
L1   : 255-0
L2   : 254-1
L3   : 253-2
L4   : 252-3   => 84-1, 84-1, 84-1
L5   : 251-4
L6   : 250-5   => 50-1, 50-1, 50-1, 50-1, 50-1
L7   : 249-6   => 83-2 x3
L8   : 248-7
L9   : 247-8
L10  : 246-9   => 82-3 x3
L11  : 245-10  => 49-2 x5
L12  : 244-11
L13  : 243-12  => 81-4 x3
...
L16  : 240-15  => 16-1 x15 / 80-5 x3 / 48-3 x5 (which one?)
L17  : 239-16
L18  : 238-17  => 14-1 x17
L19  : 237-18  => 79-6 x3
...
L21  : 235-20  => 47-4 x5

Clarification of when it's required to evenly divide a single pulse into multiple pulses must be defined. As it stands due to these complications a LUT with the pulse sequences and the shift register is probably the best choice unless there is a specific subset of discrepant increment sequences allowed. Currently there are more than 84+50+16=150 discrepant sequences out of the 256 laps, which would require special handling of each of these if this was done using a counter based approach.

I can almost envision a solution that would utilize modulo counters and specific compare patterns to determine the count values of the lap interval counter which generate increments. This is an intriguing problem and I believe it's possible to solve with a clever solution if the overlapping pattern choices can be resolved. Though clever solutions are usually not the best solutions for a job, unless they are documented well, tested thoroughly, and save significant resources compared to a simpler straight forward solution.

Regards