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How to increase PIMP (P-Implantation) area for NMOS?

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group4pgs

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I have getting DRC errors in Cadence Virtuoso about P-Imp area not being >=0.12u but I have no idea how to increase it
 

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Probably a lonely placed PTAP contact that you could make into a doublet or whatever.

DRC should take you to the location, solution is for you to decide.
 

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