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How to increase a normal MOSFET's Vds from 5V to 7V with no additional mask

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Newbie level 4
Feb 13, 2006
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A normal .5um 5V CMOS process is now available. But the circuit should be OK under 7V's Vds. I know LDMOS is one option. But I don't want to add any more mask. Anyone who knows about it? Thanks very muck!

I have made LDMOS with no additional masks but this is
in a technology where I have a whole raft of body implants
to manipulate.

If you use a N-well, non-self-aligned drain you can get to
a decent breakdown. You'll be breaking a bunch of ground
rules no doubt, unless you're not the first guy doing this
at foundry*flow. You will have some learning to do in the
field plate department (a second poly would be sweet,
aluminum will serve but its work function is probably not

In 0.5um "3.3V" technology, I've seen longer (1um) channel
and dense body ties get me past 6V. I've also seen a lot of
people struggle to get reliable 5V +5% @ 0.6um, and so I
doubt your 0.5um, 5V process is for real. Maybe it depends
on what you consider "for real".
dick_freebird, thanks for your kind reply.
I'm now trying the non-self-aligned drain to improve the VDS since no drift or LDD layer for me.
That's pull the drain active (n+) away from gate. Distance is about 0.4um. Gate length is about 0.6um.
And foundry told me I can make an experiment.
But I have no idea how the on-resistance (Rdson) will be increased.
dick_freebird, do you have such experience?

Below pls. find an example for a 6-year-old 0.18µm HV CMOS process with a second gate oxide thickness of 250Å for ≧5V transistors. Following items have to be respected:
  • min_W = min_L = 2.5µm (for a 0.18µm process!)
  • restricted Vg vs. Vdmax range (to prevent impact ionization and hot carrier injection)
View attachment 0.18um_process_HV_electrical_guidelines_p6.pdf

Please keep in mind:
  • This is an example only!
  • For your process tech. these measures can be quite different
  • In any case you have to discuss the necessary measures with your foundry and get their approval!
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