The timing is mainly depended on the code.
But you can improve your timing by set your FPGA's speed grade,
And set some constraints on I/O of your code .
If that results in shorter routes, then probably yes. In one of my projects, the Xilinx FPGA placer wanted to arrange my large multi-stage design as one big bowl of spaghetti. The result was numerous long routes and hopeless timing. So, I applied location constraints to my stages, and then the tools had no problem meeting my timing, and finished much sooner.
Alos all of the FPGA makers has app notes it calll HDL coding styles, Xilinx xas section in there ISE documentation, it is around 100 pages look there as well