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how to improve the PSRR?

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flysnows

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what is psrr peak frequency?

I have design a current reference, but it has poor PSRR .
Can anyone give me some advice on improving the PSRR.
thaks a lot.
 

wholx

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flysnows:
what kind of current source did you make?
 

sunking

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for cmos, big L can help you.
 

qslazio

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big impedance between supply node to output node can increase low frequency PSRR, for high frequency PSRR Peak you should add some decouple capacitor to decrease the load impedance seen to ground at that frequency.
 

hr_rezaee

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hi
if you design with mosfet you can place a large capacitor between gate and source of some mosfet and it increase PSRR. see Martin book.
 

qslazio

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hr_rezaee said:
hi
if you design with mosfet you can place a large capacitor between gate and source of some mosfet and it increase PSRR. see Martin book.

That is only for PMOS output stage.
When use NMOS output stage, nothing helps.
 

beckchm

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best configuration
 

hr_rezaee

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qslazio said:
That is only for PMOS output stage.
When use NMOS output stage, nothing helps.
it depends that you want to improve PSRR+ or PSRR-.
 

fnlee

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you can refer this paper:
an improved bandgap reference with high power supply rejection.(2002.ieee)
 

amic

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If i am expecting input signal at speed of 10 samples per second...should I look PSR at 10 Hz or at DC ??
Also for the folded cascode opamp with class AB stage i am getting a Power Supply rejection of -40 dB at DC which falls to -10 dB at 10Hz and eventually settles at flat responce of 0 dB after 1KHz ..?

how do i interpret it ? is it good, bad ? how do i improve it if I am already using cascode output stage ( giving high resistance betn +ve Vdd and output node )
 

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