The ultimate / theoretical performance will be limited by devices (transistors).
In reality, layout parasitics will often kill the performance, and many other characteristics (reliability, robustness, etc.).
Parasitics are especially critical in advanced nodes (16nm and lower), and in designs that are pushing the technology capabilities of the process to its edge.
Unfortunately, there are no good books that teach layout and layout parasitics.
Classical books on this topic are "The art of analog layout" by A. Hastings, and few others, but they do not teach the "real" thing.
Also, there are no good books on parasitics extraction - the only good one was "Interconnect RC and layout extraction for VLSI", but it is out of print...