How to improve the performance of the circuit?

[Collang2]

Hi, I am a college student studying CMOS VSLI DESIGN.

The best method would be to do a finer process(like a 5nm), but this is not something a circuit designer can do!

I'm trying to find as much information as possible, but if you have any good books or papers on this, please let me know!

Thank you

 

[dick_freebird]

"The" circuit? What circuit?

You're not going to, for example, "improve" the high voltage
switching performance of anything, by going to 5nm (from
where?). You might improve speed and transistors per mm2.
You might or might not improve power depending on the
balance of trade-offs made for you by the foundry and
your circuit's demands (can't have highest speed and lowest
leakage, both, at once, in multi-VT flows).

If you were for real, working on technology selection for
a real product, you'd be parsing the "care-abouts" into
device attribute requirements and then shop to the list.
Only if your interests are very narrow and your technology
choices constrained similarly, could you be so general as
to "just pick a gate length".

 

[Collang2]

Sorry. I wrote too vaguely.
I'm talking about different ways to improve the performance of circuit performance (speed, power, area, noise) etc. in cmos vsli design.

I'm not talking about a specigic CMOS circuit one, I want to study various methods of various circuits!

 

[timof]

The ultimate / theoretical performance will be limited by devices (transistors).
In reality, layout parasitics will often kill the performance, and many other characteristics (reliability, robustness, etc.).
Parasitics are especially critical in advanced nodes (16nm and lower), and in designs that are pushing the technology capabilities of the process to its edge.
Unfortunately, there are no good books that teach layout and layout parasitics.
Classical books on this topic are "The art of analog layout" by A. Hastings, and few others, but they do not teach the "real" thing.
Also, there are no good books on parasitics extraction - the only good one was "Interconnect RC and layout extraction for VLSI", but it is out of print:

Interconnect RC and Layout Extraction for VLSI: Zhu, Qing K.: 9781553953692: Amazon.com: Books

Interconnect RC and Layout Extraction for VLSI [Zhu, Qing K.] on Amazon.com. *FREE* shipping on qualifying offers. Interconnect RC and Layout Extraction for VLSI

www.amazon.com

Parasitics are affecting other properties of circuits, such as precision - e.g. leding to mismatch between the nets and devices.

 

[guntherleet]

For analog designer to migrate a circuit to more modern process (alike 5nm as you mentioned) is usually will make the circuit perform worse.
Transistors behavior much more interwind with higher order effects, and a lot of time you lose some degree of freedom with choosing the physical size of a transistor (i.e, let say a 4-fin transistor could only be with more then 4 min-width fingers).

The more small the devices get, its true that the self capacitance and parasitics will get better and its great news especially with high-speed circuits (although self-heat becomes real concern as designs become denser and speed rate increase) but the transconductance is getting worse and the flicker noise is getting much worse with each process node.

In order to improve the performance of a circuit - its tradeoff need to be fully understood and pull it towards the more important spec.

 

[timof]

"The more small the devices get, its true that the self capacitance and parasitics will get better and its great news especially with high-speed circuits"

Sorry to disappoint you - but with technology scaling, parasitics are increasing, in magnitude, number, and impact - not decreasing.

 

[guntherleet]

I was referring the device self capacitance, you correct in the sense that the overall parasitic is more dominant because structures become denser with narrower routings and contacts also because the device self capacitance getting smaller so in percentages the parasitic play more critical roll.