If I have already finished my design to provide a stable voltage reference bias to nmos and pmos , but I want to put some mos capacitors between VDD and pmos bias or between nmos bias and gnd in the layout.
I don't know if this way will works , and I have no idea if this way will bring what performance damage ?
Maybe the current bias for other cicuit is better than voltage .
Specifically the current bias is the best for long distance bias on a system chip.
The bypass capacitor of VDD and VSS is very important in bias . But u must select a right value because it work as a filter. if its value is right, it will not damage circuit performance.
Do take note of how you hook up the MOS-caps. If the voltage across the caps is smaller than Vt, you may want to put the MOS-caps in accumulation mode instead to get a better fF/um2.
True, there are some big decoupling caps for power supply off chip;
at the same time there are also some on-chip decoupling caps.
They coexist for stabilizing power supply and reducing power spikes at different regions/frequency range.
Should be good enough to just add a couple of PMOS transistors with S,D,Well tied to supply and gate tied as capacitor. Same for a couple of NMOS tarnsistor S,D,bulk tied to GND gate tied to line. This is very common in band gap layouts.