How to improve settling

[iexplorer]

how to improve settling time

I am now designing a ADC with a front end SHA, but my opamp 's GBW is really limited , especially in case of unit gain , my SHA structure is one capacitor sharing sampling and holding , so there is a huge settling time,anyway to improve the opamp settling ? Thanks

 

[skythunder]

could you please provide the details on the architecture of your OPAMP ?

 

[iexplorer]

full diff,two stage ,have a miller cap. 90db,130MHz when load 1.5pf

 

[lijianheng]

Consider more phase margin?

 

[venky442]

improve setting setting time(decreasing setting period) by maintaing the circuit in the critical rather than in either underdamping or overdamping.
for that we need to insert resistance and capacitance compensatin with increasing Resistance value and decresing the capacitance

so that we improve the setting time of opamp design

 

[Hunter_BJUT]

try to use gainboost single stage, because your two-stage contains 2 dominant pole with decrease the gain with frequency so quickly that lag your GBW.

 

[mists]

large bandwidth, appropriate phase margin and avoid pole-zero doublet