I don't like the look of that "DAC". The "resistors" are not
resistors (MOSFETs biased into conduction, expect much
nonlinearity), the virtual-ground point is not shown, the
settling time is going to suck because you're hard-banging
the current sinks and their reference rail (ought to be
"steering" current with as much finesse as practical) and
how do you figure on keeping the "R" matched when every
stage has a different Vgs (common "vb" along a varyingly-
biased ladder)?
The source of the complaints is likely the conflict between M0
with its B, S to "fk" (check yourself, not practical on a basic
one-well JI CMOS flow) and drain-commoned to M59 with its
B, S grounded. Any positive-going signal on "fk" will forward
bias M0...