Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to improve insersion loos for UWB wilkinson power divider

Status
Not open for further replies.

AmmarAli

Junior Member level 1
Joined
Mar 27, 2015
Messages
19
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
133
Hi

I am working on destining a 2:1 three stage UWB Wilkinson equal power divider for the frequency range (2-7)GHz using CST microwave studio with 50 ohm input and output impedance. The design is attached and the S parameter also.

https://obrazki.elektroda.pl/1795907800_1433768169.jpg
https://obrazki.elektroda.pl/5237299900_1433768170.jpg
https://obrazki.elektroda.pl/4503310700_1433768171.jpg


The problem:

I need to improve the insertion loos for the higher band (4-7)GHz.

Your comments and suggestions will be highly appreciated.
 

edf

Full Member level 2
Joined
Feb 21, 2002
Messages
121
Helped
21
Reputation
42
Reaction score
18
Trophy points
1,298
Activity points
700
Hi

I am working on destining a 2:1 three stage UWB Wilkinson equal power divider for the frequency range (2-7)GHz using CST microwave studio with 50 ohm input and output impedance. The design is attached and the S parameter also.

https://obrazki.elektroda.pl/1795907800_1433768169.jpg
https://obrazki.elektroda.pl/5237299900_1433768170.jpg
https://obrazki.elektroda.pl/4503310700_1433768171.jpg


The problem:

I need to improve the insertion loos for the higher band (4-7)GHz.

Your comments and suggestions will be highly appreciated.

First, make sure your TLines are 90 deg at 4.5 GHz =(2+7)/2.
Second, use real time variable tuning capabilities for the characteristic impedances.
 

AmmarAli

Junior Member level 1
Joined
Mar 27, 2015
Messages
19
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
133
First, make sure your TLines are 90 deg at 4.5 GHz =(2+7)/2.
Second, use real time variable tuning capabilities for the characteristic impedances.

Thanks edf for your reply.
I did not understand fully what you ment by "make sure your TLines are 90 deg" do you mean the connection between the input port and the first section ? if yes. I also designed other model for the power divider and cot similar insertion loss. please check the attached pic.

https://obrazki.elektroda.pl/4796521300_1433959012.jpg

If possible ... could you explain in more details how to do real time variable tuning for the characteristic impedance ? ( do you mean parameter sweep ? )

- - - Updated - - -

thanks edf for you reply.

I did not fully understand what you do you mean by "make sure your TLines are 90 deg" ... do you mean that the between the input port and the fist stage ? if yes .. I designed other power divider which is in the bellow link:
http://obrazki.elektroda.pl/4729552600_1433960880.jpg

and got the similar issue with insertion loss.
beside that could you please explain how to do the real time variable tuning for the characteristic impedance with CST ?
or you mean the parameter sweep ?
 

edf

Full Member level 2
Joined
Feb 21, 2002
Messages
121
Helped
21
Reputation
42
Reaction score
18
Trophy points
1,298
Activity points
700
Thanks edf for your reply.
I did not understand fully what you ment by "make sure your TLines are 90 deg" do you mean the connection between the input port and the first section ? if yes. I also designed other model for the power divider and cot similar insertion loss. please check the attached pic.

https://obrazki.elektroda.pl/4796521300_1433959012.jpg

If possible ... could you explain in more details how to do real time variable tuning for the characteristic impedance ? ( do you mean parameter sweep ? )

- - - Updated - - -

thanks edf for you reply.

I did not fully understand what you do you mean by "make sure your TLines are 90 deg" ... do you mean that the between the input port and the fist stage ? if yes .. I designed other power divider which is in the bellow link:
https://obrazki.elektroda.pl/4729552600_1433960880.jpg

and got the similar issue with insertion loss.
beside that could you please explain how to do the real time variable tuning for the characteristic impedance with CST ?
or you mean the parameter sweep ?

I was referring to 90deg (quarterwave) long arms in the Wilkinson splitter being at 4.5GHz. I assumed you simulated the circuit with a linear simulator first before doing the fullwave (EM) simulation. Many linear simulators have variable parameter tuning, but yes you could do a parameter sweep in the fullwave simulator. I do prefer your second layout because it doesn't pinch to a point (at resistor bridge) like the first.
 

AmmarAli

Junior Member level 1
Joined
Mar 27, 2015
Messages
19
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
133
Thanks edf for your reply.
All armed are 90deg ar 4.5 GHz.... I did parameter sweep but for several parameters but the insertion loss slightly changed .
I still do not know how increase the insertion loss.
 

volker@muehlhaus

Advanced Member level 5
Joined
Apr 11, 2014
Messages
2,572
Helped
1,002
Reputation
2,008
Reaction score
983
Trophy points
1,393
Activity points
16,575
You can check in simulation what is causing your losses:
- set the conductor to lossless (PEC) so that you see the effect of dielectric lossses only
- set the dielectric loss tangent (tand) to zero so that you see the effect of conductor losses only

If you are using FR4 substrate, you will see higher insertion loss at higher frequencies, caused by the substrate tand.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top