animeshjn is right in the case of whole case testing stage. All process mismatches will harm the CMRR, including resistor mismatch, transistor size mismatch, threshold voltage mismatch.
On the other hand, in the case of schematic simulation, process mismatches are not considered at this stage yet. CMRR is depending on your OpAmp design. For example, doing the Opamp by a differential pair with current tail, make sure the current tail (current mirror) has a very high output impedance. In the common mode, the current tail's high output impedance degenerates the common-mode gain, which results in a high CMRR.