bbqsky
Junior Member level 2
sigma delta downsampling
I am designing the decimation filter for sigma delta ADC. The filter is multi-stage and the first stage is a Sinc filter.
The implementation of the Sinc filter as a cascade of integators and differentiators, the integators operate at high clock rate, the differentiators operate at low clock rate.
Because the integator is cascaded, the second and third integators will very easy to go unlimited, if the their input is always negative or positive.
The Sinc filter is so popular using for downsampling, who can help me to realize it.
Thanks for any reply!!
I am designing the decimation filter for sigma delta ADC. The filter is multi-stage and the first stage is a Sinc filter.
The implementation of the Sinc filter as a cascade of integators and differentiators, the integators operate at high clock rate, the differentiators operate at low clock rate.
Because the integator is cascaded, the second and third integators will very easy to go unlimited, if the their input is always negative or positive.
The Sinc filter is so popular using for downsampling, who can help me to realize it.
Thanks for any reply!!