how to implement ROM in verilog code

LinXiaoling · Nov 6, 2009

Hi!
I want to implement ROM (about 64*16K) in my own verilog code.and I use the code style like this:
always@(posedge clk)
begin
if(clk_en)
begin
case(address)
0: ROM_data <= 16'd11;
1: ROM_data <= 16'd21;
...
endcase
end
end

but for my ROM_data is too large,so the ISE tool download the .v so long . and I try to realize it by IP core,but there exists the same problem,.coe download long,too. so can any guys give me some advice.Thanks!
ps: my computer is running well for big design.and for ISE9.2 and ISE11.1,the same problem.

RBB · Nov 6, 2009

This is only the fly, so no guarantees..

Code:

reg [15:0] mem [16384:0]

always @ (posedge clk)
    if(clk_en == 1'b1)
        ROM_data <= mem[address];
    else
        ROM_data <= {16{1'bx}};

LinXiaoling · Nov 6, 2009

RBB said:
This is only the fly, so no guarantees..

Code:

reg [15:0] mem [16384:0] always @ (posedge clk) if(clk_en == 1'b1) ROM_data <= mem[address]; else ROM_data <= {16{1'bx}};

Thanks anyway

how to implement ROM in verilog code

LinXiaoling

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LinXiaoling

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how to implement ROM in verilog code

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