Apr 5, 2007 #1 Y yamaha Member level 1 Joined Jan 31, 2007 Messages 38 Helped 2 Reputation 4 Reaction score 1 Trophy points 1,288 Activity points 1,495 hi how to implement open collector logic in VHDL, regards yam
Apr 5, 2007 #2 D dk614nd Advanced Member level 4 Joined Aug 8, 2006 Messages 106 Helped 46 Reputation 92 Reaction score 17 Trophy points 1,298 Activity points 1,997 Re: Open collector use and gate
Apr 5, 2007 #3 tkbits Full Member level 5 Joined Dec 4, 2004 Messages 242 Helped 39 Reputation 78 Reaction score 2 Trophy points 1,298 Activity points 2,209 Re: Open collector If you're interfacing to an external connection that requires open collector characteristics (e.g., PS/2 interface), then you can simulate open collector buffers with 3-state buffers: out_signal <= '0' when in_signal = '0' else 'Z';
Re: Open collector If you're interfacing to an external connection that requires open collector characteristics (e.g., PS/2 interface), then you can simulate open collector buffers with 3-state buffers: out_signal <= '0' when in_signal = '0' else 'Z';