franticEB
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Hi to all,
i would like to implement this kind of schematic:
is it possible to realize this kind of scheme? Are there any issues that i've not considered?
Could you suggest a similiar kind of diagram without the use of jtag programming pin?
Thanks
i would like to implement this kind of schematic:
- Power up the board with the switch closed;
- All pin are in Hi-Z (TRI-STATE)...is this true?
- With altera usb blaster i program the configuration device;
- Shut down the board and remove altera probe;
- Open switch;
- Power up the board;
- The FPGA reads configuration from the external memory.
is it possible to realize this kind of scheme? Are there any issues that i've not considered?
Could you suggest a similiar kind of diagram without the use of jtag programming pin?
Thanks