How to implement a random generator on FPGA?

[Tom2]

Is anyone who know how to implement a random generator on fpga?????

 

[anant]

Re: random test pattern

what type of pattern u want to generate?

 

[thamarai]

random test pattern

if u want to generate random number, u can generate through shift register and ex-or gate

 

[go4sandesh_vsn]

random test pattern

thts wat is called an LFSR...so u can use an LFSR...c it depends on ur appln n ur test strategy wat sort of test pattern u want

 

[khaila]

Re: random test pattern

Is anyone who know how to implement a random generator on fpga?????

Take!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity random is
port (
clk : in std_logic;
rst : in std_logic;
randomo : out std_logic_vector (7 downto 0)
);
end ;


architecture behave of random is

signal sequence_reg : std_logic_vector (15 downto 1) ;
signal xored_data : std_logic_vector (8 downto 1) ;

begin

xored_data <= sequence_reg(14 downto 7) xor sequence_reg(15 downto 8);
randomo <= xored_data ;


-------------------------------------------------------------------------------------------
randomizer : process (clk, rst)
-------------------------------------------------------------------------------------------
begin
if rst = '1' then
sequence_reg <= "000000010101001" ;
elsif (clk'event and clk = '1') then
sequence_reg(8 downto 1) <= xored_data;
sequence_reg(15 downto 9) <= sequence_reg(7 downto 1);
end if;
end process;
-------------------------------------------------------------------------------------------


I am using this VHDL code in my testbench to generatate Random Vector.

end behave;

 

[eeeraghu]

Re: random test pattern

assign feedback = ~^{x[7],x[5],x[4],x[3]};

always @(posedge clk) begin
if (reset) x <= 0;
else x <= {x[6:0], feedback};

x is the output 8 bit which generates different values each time

 

[shiv_emf]

random test pattern

u can write code in verilog n download it in fpga...