fantastic0422
Newbie level 1
Hi all: I'm designing a 10 bits 100MHz/s Pipeline ADC by using OP sharing.
I wanna change my architecture from 1.5 b/stage to 2.5b/stage due to power optimization.
But I don't know how to design the 6-to-3 encoding circuit in subADC.
Where can I find the specific schematic diagram?
Or someone can help me out !
Many thx.:-D
I wanna change my architecture from 1.5 b/stage to 2.5b/stage due to power optimization.
But I don't know how to design the 6-to-3 encoding circuit in subADC.
Where can I find the specific schematic diagram?
Or someone can help me out !
Many thx.:-D
