How to handle hold timing in FPGA .

[quan228228]

I want to know whether the 'bit' file generated by ISE must meet hold timing. If there are hold timing in FPGA , how to handle it.


Thanks!

David

 

[YenYu]

Re: HOLD time in FPGA .

I'm sure there is hold timing, but i dont know how to do it. guess this could help abit xD.

Or is it assigning like this?
x<= '1' after 1ns, '0' after 2ns ....;

 

[calm]

HOLD time in FPGA .

there are specific tool in ise for solving the setup/hold timing problem, however at the most time you need not take care of that.

 

[quan228228]

Re: HOLD time in FPGA .

there are specific tool in ise for solving the setup/hold timing problem,

calm:

Could you tell me what the specific tool is ? And Could you give me some paper about this tool or issue. Thanks!


David

 

[pramodm]

Re: HOLD time in FPGA .

when ur doing PAR in ISE, the ISE PAR tool automatically check for hold violations and gives timing report either ur design met timing requirements or not, if any violations(setup & hold) PAR fails to route ur design and reports, on which timing path violation occur