i) Will it create timing during STA(scan_mode shift)?
iii) "when doing STA, timing will be met in tet mode." What are the paths the STA has to met during test mode?
is there any other sub modes do the STA has to check timing?
- in the capture, check for the setup on 'D' path but my question is , will it not be time closed this path during "FUNCTIONAL" STA? or this has to be seperately time closed during test mode STA? Please clarify.
"ii) How should I handle the at-speed atpg for these two domains?(design has internal PLL)."
Consider the test clock = TCK which runs on ATE = 50 Mhz.
So, for a) DC scan shift = TCK and capture = TCK.
b.0) AC scan shift = TCK but capture = 80 Mhz clock
b.1) AC scan shift = TCK but capture= 500 Mhz clock
For the above point a) I think it clarifies from the past posts as we discussed. But for
points b.0 and b.1 I am not clear on this and how to handle these scenarios? Please help on these points.
a) DC scan shift = TCK and capture = TCK.
- This is for stuck-at atpg. It will be of only on capture pulse right when Sscan enable =0; Are ther any thing we can do multile capture ?
b.0) AC scan shift = TCK but capture = 80 Mhz clock
- This is for at-speed with double pulse(one launch pulse and one capture pulse) in broad side case capture clock= 80 Mhz clock.
Are there any multiple capture clock can be applied here?
b.1) AC scan shift = TCK but capture= 500 Mhz clock
- This is for at-speed with double pulse(one launch pulse and one capture pulse) in broad side case capture clock= 500Mhz clock.
Are there any multiple capture clock can be applied here?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?