kothandapani
Junior Member level 3
I have two clocks in my design one at running at 80Mhz and another at 500Mhz.
The scope is we are using single test clock for the design. So when I stritch scan (DFTA) I am putting one mux at the output of clock_gen (clk generator module) to bypass the internal generated clock. Now all the scan FFs are connected to TCK while scan_mode=1 .
i) Will it create timing during STA(scan_mode shift)?
ii) How should I handle the at-speed atpg for these two domains?(design has internal PLL).
iii)
Can you please anyone help on this?
The scope is we are using single test clock for the design. So when I stritch scan (DFTA) I am putting one mux at the output of clock_gen (clk generator module) to bypass the internal generated clock. Now all the scan FFs are connected to TCK while scan_mode=1 .
i) Will it create timing during STA(scan_mode shift)?
ii) How should I handle the at-speed atpg for these two domains?(design has internal PLL).
iii)
Can you please anyone help on this?