How to glitch-free for multiple clock?

[mitsubishi]

glitch free mux

Hi everybody,

I have four clock (osc, osc/2, osc/4, osc/8).
then i use mux to select it.
but i how to avoid glitch happen? thx.

 

[flatulent]

glitch free clock mux

Follow the mux with a D latch which is clocked from the highest speed clock.

 

[jelydonut]

glitch free clock switching

If you clock it from the fastest domain you may need to follow the mux with a syncronizer to avoid metastability. You'll just hafta take into account the delay through the syncronizer.

jelydonut

 

[flatulent]

clock mux

Another way is to use a synchronous divider following the clock and load different divide by N values. The divider will only change state in synchronism with the driving clock. This will only work if just one of the frequencies is used and not in the case where they go to other parts of the system.

 

[Arthurzss]

glitch free clock

selecting clock must use gated-clock symbol.

 

[sweesw]

glitch free clock switch

use glitch-free clock selector.
The idea is to switch the clock when the orginally selected clock line are at logic 0, wait for 2 clock cycle or so, then ramp up to the newly selected clock.

 

[bluegge]

clock mux glitch

2 dff sample selecter
one is posedge sample,one is negedge sample.

 

[seasonyangd]

how to avoid glitches

I think it depends the source of the select signal of the mux.

BTY, I dont think it is safe enough by adding a highest clocked D latch following MUX.

 

[tom123]

glitch free safe clock switching

you can try the method in the attached file.

this method is very reliable.

Hi everybody,

I have four clock (osc, osc/2, osc/4, osc/8).
then i use mux to select it.
but i how to avoid glitch happen? thx.

 

[nemolee]

muxed clock not working

module clk_gen (
dck,

pg_en,
en1ch,
lvds_dck,
lvds_dck_div2,
osc_dck,
rst_n
);

output dck;

input pg_en;
input en1ch;
input lvds_dck;
input lvds_dck_div2;
input osc_dck;
input rst_n;

reg sel_a;
reg sel_b;
reg sel_c;
reg mux_sel_1_d;
reg mux_sel_0_d;
reg mux_sel_0_d2;
reg dck;
wire [2:0] mux_sel;

always @(mux_sel or lvds_dck or lvds_dck_div2 or osc_dck)
begin
case (mux_sel[2:0])
3'b001: dck = lvds_dck;
3'b010: dck = lvds_dck_div2;
3'b100: dck = osc_dck;
default: dck = 0;
endcase
end

//--------------------------------------------
always @(negedge lvds_dck or negedge rst_n)
begin
if (!rst_n)
sel_a <= #1 1'b0;
else
sel_a <= #1 (pg_en | en1ch);
end

always @(negedge lvds_dck or negedge rst_n)
begin
if (!rst_n)
mux_sel_1_d <= #1 1'b0;
else
mux_sel_1_d <= #1 (|mux_sel[2:1]);
end

assign mux_sel[0] = ~(sel_a | mux_sel_1_d);

//--------------------------------------------
always @(negedge lvds_dck_div2 or negedge rst_n)
begin
if (!rst_n)
sel_b <= #1 1'b0;
else
sel_b <= #1 (!pg_en && en1ch);
end

always @(negedge lvds_dck_div2 or negedge rst_n)
begin
if (!rst_n)
mux_sel_0_d <= #1 1'b0;
else
mux_sel_0_d <= #1 (mux_sel[2] | mux_sel[0]);
end

assign mux_sel[1] = ~(~sel_b | mux_sel_0_d);

//--------------------------------------------
always @(negedge osc_dck or negedge rst_n)
begin
if (!rst_n)
sel_c <= #1 1'b0;
else
sel_c <= #1 pg_en;
end

always @(negedge osc_dck or negedge rst_n)
begin
if (!rst_n)
mux_sel_0_d2 <= #1 1'b0;
else
mux_sel_0_d2 <= #1 (|mux_sel[1:0]);
end

assign mux_sel[2] = ~(~sel_c | mux_sel_0_d2);


endmodule