Sep 22, 2010 #1 moonnightingale Full Member level 6 Joined Sep 17, 2009 Messages 362 Helped 5 Reputation 10 Reaction score 5 Trophy points 1,298 Activity points 3,832 I have written this code in xilinx module mux(mux_out,data_1,data_2,select); parameter word_size=32; output [word_size-1:0] mux_out; input [word_size-1:0] data_1,data_2; input select; assign mux_out=select?data_1:data_2; endmodule I am able to synthesize and view RTL Schematic but i will be highly grateful if some body tells me the method that how can i feed input to it and see the actual result and waveform. Kindly explain in detail
I have written this code in xilinx module mux(mux_out,data_1,data_2,select); parameter word_size=32; output [word_size-1:0] mux_out; input [word_size-1:0] data_1,data_2; input select; assign mux_out=select?data_1:data_2; endmodule I am able to synthesize and view RTL Schematic but i will be highly grateful if some body tells me the method that how can i feed input to it and see the actual result and waveform. Kindly explain in detail
Sep 22, 2010 #2 P permute Advanced Member level 3 Joined Jul 16, 2010 Messages 918 Helped 295 Reputation 590 Reaction score 266 Trophy points 1,343 Activity points 8,543 write a testbench. look online for examples. from there you can use a simulator. isim is included with ISE Webpack.
write a testbench. look online for examples. from there you can use a simulator. isim is included with ISE Webpack.
Sep 22, 2010 #3 moonnightingale Full Member level 6 Joined Sep 17, 2009 Messages 362 Helped 5 Reputation 10 Reaction score 5 Trophy points 1,298 Activity points 3,832 I have no idea what is test bench Can u do explain all these to me with this simple example module bitcompar(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1); input A0,A1,B0,B1; output A_lt_B,A_gt_B,A_eq_B; assign A_lt_B=({A1,A0}<{B1,B0}); assign A_gt_B=({A1,A0}>{B1,B0}); assign A_eq_B=({A1,A0}=={B1,B0}); endmodule how can i check it
I have no idea what is test bench Can u do explain all these to me with this simple example module bitcompar(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1); input A0,A1,B0,B1; output A_lt_B,A_gt_B,A_eq_B; assign A_lt_B=({A1,A0}<{B1,B0}); assign A_gt_B=({A1,A0}>{B1,B0}); assign A_eq_B=({A1,A0}=={B1,B0}); endmodule how can i check it
Sep 22, 2010 #4 J Jack// ani Advanced Member level 3 Joined Dec 2, 2004 Messages 757 Helped 107 Reputation 222 Reaction score 58 Trophy points 1,308 Activity points 5,006 This should you to get it right: Art of Writing TestBenches Part - I