measuring output impedance lvds driver r0
Hallo Frank,
yes that's correct - I have found nothing similar in TIA 644. Anyway that is also quite suprising to me because if you hardly any common-mode-signal termination than you just rely on the damping of the line for disturbances.
Meanwhile I figured out that you can use for real world application quite successful for disturbances up to 100 MHz the common-mode-feedback circuit if you apply it to the lower and the upper current source so that you get something like a symmetrical ota-structure with a output brach which is degenerated by resistors (which will generate an additional pole - but this is due to the low impedance of the switches very high frequency). In this manner you can adpat the common-mode-termination resistance towards the desired 50 ohm (20 mS) by the gm of the input-transistors of the symmetrical ota feedback circuit.
Furtheron I used internal resistors for TX-side differential signal termination - in this way I was able to split the low resistance 100 ohm differential termination resistor into two parts in order to "detect" the common-mode-signal for the feedback. As you need anyway a cap for compensating the feedback circuit you can also use this cap to have a termination for higher frequency signals (in my case around 250 MHz) as the cap gets quite low impedance for commonmode signals in this frequency range so that you will get for this range the desired 50 ohm common-mode termination just with an internal mosfet capacitor.
In this way I was able to realize some -10 dB damping for the reflection of common-mode-signals from "dc" way beyound the first harmonic of my differential data signal. Above that (500+MHz) in my case skin effect and dielectric losses of the line I use do their job in order to damp common-mode interference sufficiently ...
That's the way I do it right now - took yome time to get there - and maybe it's not the best way in one or another respect (yes, differential termination on the TX-side draws additional current - and this doesn't make the mosfet-switches smaller - and of course by this the input-capacitance of the switches - and by this the amount of power that you need for the predriver) - so let me know if you know better ways
Added after 18 minutes:
One further remark - I still have a problem with the switching.
In my LVDS TX I use as switches for the two upper switches pmos devices and for the lower two nmos devices. The reason to choose this configuration and not four nmos devices is that I ran into trouble because I have no triple well process and in this way the bodyeffect and vth-change over corners created quite some annoying overswinging in worst-speed (slow/slow) corners. The reason for that is that imo by the vth- and gamma-change you get different timings of the switching and ron over time and by this I might more or less drive the bias crcuit shortly down during switching. I was unable to solve this behaviuor over all corners without heavy skew in other corners ...
(yes I tried to have overlapping input-signals for the two switches)
The pmos/nmos configuration imo is better in this respect - as you have something like two opposite diffpairs after all ...
But also with this configuration I still have some issues with assymetric rise and fall times ...
Interestingly I get the best results when I just drive the "switches" in saturation and not realy into subthreshold/off and vice versa the linear-state. This is more or less understandabe as this is similar to the way a "real" cml-buffer also works and gets its fast switching behaviour.
The drawback of course is that over pvt-corners this degenerates due to some leakage in the "off"-transistor the amplitude of the differential signal - something which you won't have to cope with when you drive the switch-mosfest deep into linear/subtreshold region.
Another advantage is that it seems to me that I can use quite small devices - so that I can save some power in my predriver-circuit - anyway the predriver for this way of "steering" the driver doesn't allow to have inverters as a predriver because you need a level-shifted amplitude-limited input signal for the output-driver.
This is done in my circuit by a cml-buffer with common-mode-shifting-resitor and some pvt-compenstion - in order to have a fixed level-shifting and output amplitude. But what remains diffcult is that you have to go from a cmos (0 to 3.3v) input data-signal to the cml-buffer level without generating two much distortion and skew because in my digital library there are no cml latches and flipflops
...
Maybe you might say that some of the issues that I had are not an issue for a 100 or 200 MBit LVDS - driver that's correct - but if you go to 500/622 Mbit and above - and have to cope with symmetric slewrates of up to 500MV/s in order to get 300ps risetime with skew in the 100ps range over pvt than I think at least - these are issues ...
If you have comments - do me a favor and post them