Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to get output impedance requested by IEEE 1596? ( LVDS)

Not open for further replies.


Member level 5
Apr 25, 2005
Reaction score
Trophy points
Activity points

the IEEE 1596 standard requests a 40 to 140 ohm single ended output impedannce of the TX part.

I'm wondering how this can be done with a pmos (from vdd) and a nmos current source (to gnd) in the driver structure ???

ieee lvds

Did not understand ur problem clearly..

lvds reflection

ok - I anticipate that it's quite clear - what a termination resitance means - and that in the case of the IEEE1596-standard it should be between 40 to 140 ohm for a 50 ohm single line - we can discuss this if it's needed.

My problem is now that the LVDS driver consists of two current sources which drive a current through a differential termination resitance on the RX side.
It should be evident that the PMOS and the NMOS that form the current sources are working in saturation - so the internal resitance (let's assume it's gd for small signals) of the current source is quite high - several 10k to 100k ohm. This topology of the LVDS driver on the other hand allows simply no "shunt" termination to "vdd" / "gnd" of 40 to 140 ohm - there is no chance to reduce the gd of the current source Mosfets in saturation to this value ...

So I would realy like to know - how the heck do the guys from the IEEE ask for 40-140 ohm as a termination ? (when they want a current mode approach ?)

Added after 20 seconds:

clear enough ?

Added after 16 minutes:

just another addition for the understanding - without the request for the single-line termination there will be reflection coefficients of nearly 100% on both sides (the receiver and the transmitter side - not so good - isn't it ?


If the 100 ohm termination resistor on RX side match the LVDS channel impedance, then there is no reflection from RX side. But if not, then there will be 2nd reflection on TX side, and this 2nd reflection will come back to RX. So for some high-speed LVDS transmitter (>1Gbps), the TX side do implement 100 ohm differential termination resistor to reduce the 2nd reflection. But the penality is that you have to drive more current for the same swing.

lvds ieee

yeah -but that's all right - but the guys from IEEE ask for singl-ended (!!!) termination - (so termination not just for differential signals) - also for common-mode-signals ...

and then you get in real trouble - don't you ;) ?

lvds specs 300ps at 1gbps

If you want to do the single-end termination on TX side. One of the method is to use the source follower on the driving side, and the other side you can use switching resistor. In order to control the impedance, you must design some kind of tracking ckt on the driving side such that the ON resistance can be well-controlled, and at the same time this tracking ckt can control the output common-mode voltage,too.

lvds ;specification;eia

The IEEE standard specifies verry clear how to check these values. I dont think there is a problem there.

damping resistor on lvds

yes the ieee states some testing measures - but come on - they have a 33nF load for testing ;) - if you let this load see an active feedback circuit - you will detoriate the way the feedback works so much that you will realy get nothing what is of any use ...

lvds driver symmetric rise fall time


obviously, most manufacturers refer to EIA-644A rather than IEEE 1596 in LVDS specification. If I understand right, they not necessarily share the IEEE idea of 40 - 140 single ended RO, or do you know what EIA 644 demands in this repect?

Other parameters, particularly the tight specification of output offset and minimum and maximum differential voltage seems basically identical.


measuring output impedance lvds driver r0

Hallo Frank, ;)

yes that's correct - I have found nothing similar in TIA 644. Anyway that is also quite suprising to me because if you hardly any common-mode-signal termination than you just rely on the damping of the line for disturbances.

Meanwhile I figured out that you can use for real world application quite successful for disturbances up to 100 MHz the common-mode-feedback circuit if you apply it to the lower and the upper current source so that you get something like a symmetrical ota-structure with a output brach which is degenerated by resistors (which will generate an additional pole - but this is due to the low impedance of the switches very high frequency). In this manner you can adpat the common-mode-termination resistance towards the desired 50 ohm (20 mS) by the gm of the input-transistors of the symmetrical ota feedback circuit.

Furtheron I used internal resistors for TX-side differential signal termination - in this way I was able to split the low resistance 100 ohm differential termination resistor into two parts in order to "detect" the common-mode-signal for the feedback. As you need anyway a cap for compensating the feedback circuit you can also use this cap to have a termination for higher frequency signals (in my case around 250 MHz) as the cap gets quite low impedance for commonmode signals in this frequency range so that you will get for this range the desired 50 ohm common-mode termination just with an internal mosfet capacitor.

In this way I was able to realize some -10 dB damping for the reflection of common-mode-signals from "dc" way beyound the first harmonic of my differential data signal. Above that (500+MHz) in my case skin effect and dielectric losses of the line I use do their job in order to damp common-mode interference sufficiently ...

That's the way I do it right now - took yome time to get there - and maybe it's not the best way in one or another respect (yes, differential termination on the TX-side draws additional current - and this doesn't make the mosfet-switches smaller - and of course by this the input-capacitance of the switches - and by this the amount of power that you need for the predriver) - so let me know if you know better ways ;)

Added after 18 minutes:

One further remark - I still have a problem with the switching.

In my LVDS TX I use as switches for the two upper switches pmos devices and for the lower two nmos devices. The reason to choose this configuration and not four nmos devices is that I ran into trouble because I have no triple well process and in this way the bodyeffect and vth-change over corners created quite some annoying overswinging in worst-speed (slow/slow) corners. The reason for that is that imo by the vth- and gamma-change you get different timings of the switching and ron over time and by this I might more or less drive the bias crcuit shortly down during switching. I was unable to solve this behaviuor over all corners without heavy skew in other corners ...
(yes I tried to have overlapping input-signals for the two switches)

The pmos/nmos configuration imo is better in this respect - as you have something like two opposite diffpairs after all ...
But also with this configuration I still have some issues with assymetric rise and fall times ...
Interestingly I get the best results when I just drive the "switches" in saturation and not realy into subthreshold/off and vice versa the linear-state. This is more or less understandabe as this is similar to the way a "real" cml-buffer also works and gets its fast switching behaviour.
The drawback of course is that over pvt-corners this degenerates due to some leakage in the "off"-transistor the amplitude of the differential signal - something which you won't have to cope with when you drive the switch-mosfest deep into linear/subtreshold region.
Another advantage is that it seems to me that I can use quite small devices - so that I can save some power in my predriver-circuit - anyway the predriver for this way of "steering" the driver doesn't allow to have inverters as a predriver because you need a level-shifted amplitude-limited input signal for the output-driver.
This is done in my circuit by a cml-buffer with common-mode-shifting-resitor and some pvt-compenstion - in order to have a fixed level-shifting and output amplitude. But what remains diffcult is that you have to go from a cmos (0 to 3.3v) input data-signal to the cml-buffer level without generating two much distortion and skew because in my digital library there are no cml latches and flipflops ;) ...

Maybe you might say that some of the issues that I had are not an issue for a 100 or 200 MBit LVDS - driver that's correct - but if you go to 500/622 Mbit and above - and have to cope with symmetric slewrates of up to 500MV/s in order to get 300ps risetime with skew in the 100ps range over pvt than I think at least - these are issues ...

If you have comments - do me a favor and post them ;)

ieee lvds-tx specification


thank you for the detailed response. Personally I'm not engaged with IC design, I see the problem from an IC user perspective. I also think, that dedicated LVDS driver chips are mostly using the symmetrical current source design with common mode feedback amp.

With an Altera Stratix II LVDS driver, I could observe a high differential output impedance (> 1000 ohms) and the effect of an active circuit maintaining common mode voltage in case of unsymmetrical load with about 5 ns time constant. From different output differential with both output states, the feedback circuit seems to be asymmetric, apparently controlling the lower current source only.

It's noticeable, that the datasheet doesn't specify common mode properties execpt standard TIA 644 parameters offset and a residual delta voltage.

I think, the most important effect of a driver real output impedance demanded by IEEE 1596 in contrast to the usual switched current implementation would be damping of reflected differential signal. This could better be achieved by parallel differential termination as it's generally used with gigabit serial standards.

In this comparison, your design seems to belong to the high performance gigabit class. I think however, that for an FPGA mit above 100 LVDS drivers, power consumption is probably a more important demand than a possible minor improvement of signal quality with differential driver termination. Thus Altera (and most likely other manufacturers) reserve driver termination for gigabit transceiver.


Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to