agump
Member level 2
clock generator adjustable frequency
My project need to supply a frequency-adjustable clock to a ADC , and require the clock's jitter less than 10ps.At the same time , we need put a copy of the clock to a FPGA which receives datas from the ADC. Now I know I can use VCO controlled by PLL to get low jitter clock , and I can use a multi-output low-jitter clock buffer to get all the clock that I needed. Can I get the desired clock with high jitter clock as the input of the multi-output low jitter clock buffer?Please give your comments.Thanks a lot.
Best RGDS
My project need to supply a frequency-adjustable clock to a ADC , and require the clock's jitter less than 10ps.At the same time , we need put a copy of the clock to a FPGA which receives datas from the ADC. Now I know I can use VCO controlled by PLL to get low jitter clock , and I can use a multi-output low-jitter clock buffer to get all the clock that I needed. Can I get the desired clock with high jitter clock as the input of the multi-output low jitter clock buffer?Please give your comments.Thanks a lot.
Best RGDS