ronialeonheart
Junior Member level 1
I have tried to add 'fnl' in .simrc file. And the output netlist's pin is set by cadence itself. For example: the pin I set in the schematic is VDD, but in the netlist it becomes n3. And there is a sentence also: EQUA n3=/VDD. Why?
I also tried to get flat netlist by setting the simulator of "HspiceS", and the netlist type of "flat". However, from simulation-netlist-final netlist, it said there are errors: can't recognize the MOS model, even after I had add the model file. I have get hierachical netlist from the same schematic before. Who can tell me why?
Thank you!
I also tried to get flat netlist by setting the simulator of "HspiceS", and the netlist type of "flat". However, from simulation-netlist-final netlist, it said there are errors: can't recognize the MOS model, even after I had add the model file. I have get hierachical netlist from the same schematic before. Who can tell me why?
Thank you!