Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to get flat netlist by cadence?

Status
Not open for further replies.

ronialeonheart

Junior Member level 1
Joined
Aug 7, 2006
Messages
15
Helped
3
Reputation
6
Reaction score
0
Trophy points
1,281
Activity points
1,352
I have tried to add 'fnl' in .simrc file. And the output netlist's pin is set by cadence itself. For example: the pin I set in the schematic is VDD, but in the netlist it becomes n3. And there is a sentence also: EQUA n3=/VDD. Why?
I also tried to get flat netlist by setting the simulator of "HspiceS", and the netlist type of "flat". However, from simulation-netlist-final netlist, it said there are errors: can't recognize the MOS model, even after I had add the model file. I have get hierachical netlist from the same schematic before. Who can tell me why?
Thank you!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top