How to get deep hierarchy signals in top entity in NC-VHDL?

[roger]

init_signal_spy modelsim

in verilog we can use
wire signal=top.module1.module2.signal;

in modelsim we can use
init_signal_spy("../.../signal", signal1);

But in NC-VHDL
how can we got internal signal rather than using port mapping?

Help me please

 

[roger]

init_signal_spy cadance

see pdf ncvhdl.pdf

C:\Program Files\Cadence Design Systems\LDV\doc\ncvhdl

ncvhdl.pdf utilities nc_mirror

 

[sajeev_antony]

init_signal_spy

I downloaded the signal_spy packeg from model.com.
could u pls explain me where to put those files and how to use it.

in verilog we can use
wire signal=top.module1.module2.signal;

in modelsim we can use
init_signal_spy("../.../signal", signal1);

But in NC-VHDL
how can we got internal signal rather than using port mapping?

Help me please

 

[roger]

modelsim hierarchy

how to use it

add the lib header

library modelsim.lib;
use modelsim_liob.util.all;

...
...
begin

init_signal_spy("??/??/??","signal_name",0);

you canrefer to the modelsim user manual