How to generate the latch/reset signal in a pipelined ADC?

[nxing]

clocks in pipelined ADC

Hello everyone,

I am designing a pipelined ADC with 1.5bit per stage and I am using the dynamic comparator. the system has two non-overlapping clock for operating properly. However, I don't know how to generate the latch/reset signal for comparator. Can anybody give me some advice? (my systme is almost following the structure of Thomas Cho's thesis at Berkeley).

Thanks

 

[mitgrace]

clocks in pipelined ADC

YOu can reference Abo thesis .at Berkeley , It have more information for nooverlap clock

 

[shiowjyh]

Re: clocks in pipelined ADC

Basically, the latch enables at the moment of sampling phase...
And the reset should be the other way opposite...
The latch period doesn't has to last as long as sampling pulse, but acquires right one after comparator is settled.
Also, don't mess up if you are using ping-pong architecture.

Regards,

 

[nxing]

Re: clocks in pipelined ADC

Thanks for your guys' answer!
Shiowjyh, would you please tell me what's ping-pong architecture and what's special about it?

Thanks!

 

[shiowjyh]

Re: clocks in pipelined ADC

The ping-pong architecture usually been used in high speed pipeline A/D converter...
Its conversion time would be n*clock, n equals to your pipeline stage.
Basically, each stage does represent both sample and hold at a certain non-overlap clock...
It also means that you need two identical switched capacitors...

Please also refer to the following link...

**broken link removed**

Regards,

 

[bastos4321]

Re: clocks in pipelined ADC

Use a clock generator for all the phases. Usualy the clock generator generate 6 phases all nonoverlap. Two phases are to define the sampling instant, the other two are a little larger for settling of the amplifiers. The last two are the latch phases that have their position between the sampling instante and the end of the settling phase (usualy 1-3ns). This is necessay to garanty that the latch does not disturb the sampling instant by any kick back noise.

Bastos

 

[nxing]

Re: clocks in pipelined ADC

Hi Bastos

Thanks for you reply. the attachment is my timing diagram, Can you help me to figure out whether or not it's correct?

Regards,

 

[bastos4321]

Re: clocks in pipelined ADC

The sampling phases and latch are correct, but the settling phase usually extents to the end of the latch phase to guarantie a contant signal with enougth time for the comparators. Give a non overlap for all the phases of at least 200ps.

Good luck Bastos

 

[nxing]

Re: clocks in pipelined ADC

So, basically, the latch phase and the settling phase are not non-overlanpped. Isn't it?

Regards

 

[mady79]

Re: clocks in pipelined ADC

I have one question ,how does one decide on the latch time
period or when would the latch time would start ? .Let's say 20ns(sampling time=10ns,Hold time=10ns) is the time period ,then when would the latch time start in sampling time ?

Comparator makes the decision in this latch time and I think this decisions need to be stored until the residue is calculated for that stage or else extend latch1 till the end of the hold1.

Please get back to me .
Thanks in Advance.

 

[nxing]

Re: clocks in pipelined ADC

Actually, I made the latch phase is almost half length of holding time(delay around 5ns), which give enough time for the residue amp to settle down with the final value.

Hope it's helpful!

Regards,

 

[mady79]

Re: clocks in pipelined ADC

But if u look into the schematic of the dynamic comparator ,once the latch1 becomes zero , the output of the comparator goes to VDD level.So ,we have to store or retail the comparator outputs .

Let me know what you have done .












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[nxing]

Re: clocks in pipelined ADC

You can put a flip-flop at the output of comparator and store it's value when latch is high. I put a D-FF and it works.

 

[bastos4321]

Re: clocks in pipelined ADC

yes, the latch phase and the settling phase are not non-overlapped.

The latch duration is only the time for the comparator to decide, and usually is 1-2ns or even less in high speed adcs.

The comparator have a latch at its output witch hold the value till the next latch signal. This means that you could sample to a flipflop the latch after the latch phase goes down.

Good luck Bastos