How to generate sine waves using verilog?

[keerthna]

How to generate sine waves by using a verilog code? Can anyone please explain in detail? I heard about the look up table but have no clue on how to implement on FPGA? Can anyone post a sample code to help ?
Thanks in advance

 

[mrflibble]

Your local friendly vendor will typically offer IP for that. See for example: https://www.xilinx.com/products/intellectual-property/dds_compiler.html

 

[keerthna]

How do i know if my FPGA supports such an ip core or not?

 

[mrflibble]

By reading the documentation of the fpga vendor? Anyways, Xilinx & Altera both offer DDS cores. So if you use Xilinx you already had your answer in post #2. If you use Altera you now have your answer in post #4. And if you use another fpga vendor then post #5 is an excellent place to mention which fpga you are using. ;-)

 

[keerthna]

I use spartan-6 FPGA from xilinx

 

[mrflibble]

So if you use Xilinx you already had your answer in post #2.

I use spartan-6 FPGA from xilinx

Problem solved then. ;-)

 

[FvM]

I assume the Xilinx DDS generator isn't available in the free ISE/Vivado WebPack version?

 

[mrflibble]

Well, I just checked my webpack Vivado install and I could use the DDS Compiler without problems. And I recall a similar situation with ISE for webpack.

 

[FvM]

Good. Advantage Xilinx versus Altera.