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In your waveform, no clamping action can be seen. But it looks rather like a simulation waveform (with a fictive zero impedance signal source) than a real world measurement.
Without knowing the time scale of the waveforms, you can't see much from it. It's unclear however, why the DC level at VF1 seems to be constant. Seems like the waveform belongs to a partly different circuit (e.g. with an additional output load).
Generally, the OP output impedance is obviously too high to work as a voltage source here, apparently the output is driven into current limit. But without at a current limited signal, clamping can't work, even if you put in a high speed OP, that can source 100 mA and more. To design a suitable circuit, a meaningful specification of the clamping operation would be needed first.
It's not how a real circuit is expected to be behave (also considering the problems mentioned above). If you post
your TINA file, someone can try to find what's wrong with the simulation setup or involved devices.