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How to generate negative constant voltage source?

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EDA_hg81

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I can generate positive voltage source.

How can I generate negative voltage source?

Thanks.
 

bill66656

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In PWM converter group, exchange the node connection of VREF and VSS. then VOUT will be forced negatively.
 

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FvM

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The answer strongly depends on your method to generate a positive voltage source...
 

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bobcat1

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Hi

From the practical point of view if you need a negative voltage source to drive an opamp all you need is to add A max232 IC and connect the driver output to the amp neg power rails.

All the best

Bobi
 

    EDA_hg81

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EDA_hg81

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Here is the situation I met:

I am building a voltage clamper based on follow drawing.

I used two OPA735 to generate -2V reference for realizing negative voltage clamper.

I got the fine output signals at VF1.

But the problem is the voltage at VF4 is not fixed at -2V since the current flow through diode, it is variable and follows the output signals.

I tried use current mirror, the same result.

Is it ok?
 

FvM

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The topic illustrates in a wonderful way, what you can get by putting highly ambiguous questions :D.

I got the fine output signals at VF1.
In your waveform, no clamping action can be seen. But it looks rather like a simulation waveform (with a fictive zero impedance signal source) than a real world measurement.

Without knowing the time scale of the waveforms, you can't see much from it. It's unclear however, why the DC level at VF1 seems to be constant. Seems like the waveform belongs to a partly different circuit (e.g. with an additional output load).

Generally, the OP output impedance is obviously too high to work as a voltage source here, apparently the output is driven into current limit. But without at a current limited signal, clamping can't work, even if you put in a high speed OP, that can source 100 mA and more. To design a suitable circuit, a meaningful specification of the clamping operation would be needed first.
 

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EDA_hg81

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the waveform is from TINA, the frequency is 40MHZ.

The input signal is from 0V to 5V, The output at VF1, which is the only output, is shifted down 2V.

I want to clamp this signal to -2V to +3V.
 

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A 1.6 MHz GBW OP can't work as a voltage source at 40 MHz. Also a 4A power rectifier isn't suitable as clamp diode.

Because your circuit (if working correctly) limits the most positive voltage, the clamping level must be +3V not -2V.
 

    EDA_hg81

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EDA_hg81

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I did simulation again without that opamp voltage source and with different diodes.

The following drawing show the results, the VF2 waveform is the input signal in front of CAP, VF2 is the signal after CAP.

You can see signal at VF1 is never pulled down to -5V?

The value of CAP is 100n.

Why?
 

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It's not how a real circuit is expected to be behave (also considering the problems mentioned above). If you post
your TINA file, someone can try to find what's wrong with the simulation setup or involved devices.
 

    EDA_hg81

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EDA_hg81

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I know it is not normal. But I can't post all circuit here.

I think I found where is wrong.

The pulses I generated is 6ns width but the diode can't turn on and off so fast.

I have replaced the diode clamper with opamp clamper.

It function well but the pulse edge is not too sharp.

FVM if you want TINA circuit, I can send it to you.
 

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