How to generate Gaussian noise using vhdl that will be synthesizable?

[Anwesa Roy]

We are trying to generate Gaussian noise using vhdl. We have found a code that uses real variables to generate Gaussian noise and hence not synthesizable which is given here:

https://kanyevsky.kpi.ua/fpgadesign/dsp_rab1e.html

. Please post a code so that we can generate Gaussian noise using vhdl that is synthesizable.

The non synthesisable code is givenbelow. You may also mention the portions that we can edit in this program to make it synthesisable.

library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.math_real.all;
 entity Gauss_Gen is
  generic(nn:natural:=1; --power of the binomial distribution <16
  m:REAL:=0.0    -- mean output value
    );
   port(
    CLK : in STD_LOGIC;
    RST : in STD_LOGIC;
    DATA_OUT : out REAL:=0.0
    );
   end Gauss_Gen;
 architecture Model of Gauss_Gen is
        type arri is array (0 to 15) of integer;
        type arrr is array (0 to 15) of real;
 begin
 SFR:process(clk,rst)
  variable s1:arri:=(3,33,333,3,4,5,6,7,8,9,11,22,33,others=>55);
  variable s2:arri:=(5,55,555,50,6,7,8,9,5,6,7,21,33,others=>22);
  variable r:arrr:=(others=>0.0);
  variable s:real:=0.0;
        begin
           if rst='1' then
              DATA_OUT<=0.0;
           elsif  clk='1' and clk'event then
        s:=0.0;
        for i in 0 to nn-1 loop    -- nn noise generators
                   UNIFORM (s1(i),s2(i),r(i));
                   s:=s+r(i);
        end loop;
            DATA_OUT <= 2.0*(s/real(nn)-0.5)+ m;
           end if;
      end process;
  end Model;

 

[dpaul]

Please post a code so that we can generate Gaussian noise using vhdl that is synthesizable.
The non synthesisable code is givenbelow. You may also mention the portions that we can edit in this program to make it synthesisable.

That's like asking to do the homework.

I am providing an alternative!

Can't you not translate the concept presented here into VHDL:
https://hal.inria.fr/file/index/docid/347213/filename/ICECS_00_Emul.pdf

A VHDL snippet is also provided in the Annex of this paper.

btw- What was the outcome of your previous post?
https://www.edaboard.com/threads/357461/

 

[Anwesa Roy]

That's like asking to do the homework.

I am providing an alternative!

Can't you not translate the concept presented here into VHDL:
https://hal.inria.fr/file/index/docid/347213/filename/ICECS_00_Emul.pdf

A VHDL snippet is also provided in the Annex of this paper.

btw- What was the outcome of your previous post?
https://www.edaboard.com/threads/357461/

Sir we were successful in adding pseudorandom noise sequence to our sine wave, but now we are trying to add Gaussian noise. The code and the simulation results for ADDITION OF PSEUDORANDOM NOISE SEQUENCE TO SINE WAVE IS GIVEN BELOW:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;  --try to use this library as much as possible.

entity sine_wave is
 generic ( width : integer :=  4 ); 
port (clk :in  std_logic;
      random_num : out std_logic_vector (width-1 downto 0); 
      data_out : out STD_LOGIC_VECTOR(7 downto 0)
      );
end sine_wave;

architecture Behavioral of sine_wave is
signal data_out1,rand_temp1,noisy_signal : integer;
signal noisy_signal1 : STD_LOGIC_VECTOR(7 downto 0);
signal i : integer range 0 to 29:=0;
--type memory_type is array (0 to 29) of integer;
type memory_type is array (0 to 29) of std_logic_vector(7 downto 0); 
--ROM for storing the sine values generated by MATLAB.
signal sine : memory_type :=("01001101","01011101","01101100","01111010","10000111","10010000","10010111","10011010","10011010","10010111","10010000","10000111","01111010","01101100","01011101","01001101",
"00111101","00101110","00100000","00010011","00001010","00000011","00000000","00000000","00000011","00001010","00010011","00100000","00101110","00111101");
--hi
begin

process(clk)
variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');
variable temp : std_logic := '0';
begin
  --to check the rising edge of the clock signal
if(rising_edge(clk)) then  

temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
   
--data_out <= sine(i);
i <= i+ 1;
if(i = 29) then
i <= 0;
end if;
end if;
data_out <= sine(i);
data_out1<=to_integer(unsigned(sine(i)));
random_num <= rand_temp;
rand_temp1<=to_integer(unsigned(rand_temp));
noisy_signal<=data_out1+rand_temp1;
noisy_signal1<= std_logic_vector(to_signed(noisy_signal,8));
end process;

end Behavioral;

Also we were able to add Gaussian noise to the sine wave. But that was only visible in simulation, it cant be synthesized.The code and simulation results for the same is given below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;  --try to use this library as much as possible.
 use IEEE.math_real.all;
 

entity sine_wave is

 generic(nn:natural:=1; --power of the binomial distribution <16
   m:REAL:=0.0     -- mean output value
     );
     
port (clk :in  std_logic;
      data_out : out STD_LOGIC_VECTOR(7 downto 0);
      DATA_OUTT : out REAL:=0.0
      );
end sine_wave;

architecture Behavioral of sine_wave is

type arri is array (0 to 15) of integer;
type arrr is array (0 to 15) of real;

signal data_out1 :  STD_LOGIC_VECTOR(7 downto 0);
signal	noisy_signal,DATA_OUTTT : real;
signal i : integer range 0 to 29:=0;
--type memory_type is array (0 to 29) of integer;
type memory_type is array (0 to 29) of std_logic_vector(7 downto 0); 
--ROM for storing the sine values generated by MATLAB.
signal sine : memory_type :=("01001101","01011101","01101100","01111010","10000111","10010000","10010111","10011010","10011010","10010111","10010000","10000111","01111010","01101100","01011101","01001101",
"00111101","00101110","00100000","00010011","00001010","00000011","00000000","00000000","00000011","00001010","00010011","00100000","00101110","00111101");
--hi
begin

process(clk)
 variable s1:arri:=(3,33,333,3,4,5,6,7,8,9,11,22,33,others=>55);
 variable s2:arri:=(5,55,555,50,6,7,8,9,5,6,7,21,33,others=>22);
 variable r:arrr:=(others=>0.0);
 variable s:real:=0.0;
begin
  --to check the rising edge of the clock signal
if(rising_edge(clk)) then 

s:=0.0;
       	for i in 0 to nn-1 loop    -- nn noise generators
                   UNIFORM (s1(i),s2(i),r(i));
                   s:=s+r(i);
       	end loop;
        	DATA_OUTT <= 2.0*(s/real(nn)-0.5)+ m;
            DATA_OUTTT <= 2.0*(s/real(nn)-0.5)+ m; 
    
data_out <= sine(i);
data_out1 <= sine(i);
--noisy_signal<=real(to_integer(unsigned(data_out1)))+DATA_OUTTT;
i <= i+ 1;
if(i = 29) then
i <= 0;
end if;
end if;
end process;
noisy_signal<=real(to_integer(unsigned(data_out1)))+DATA_OUTTT;
end Behavioral;

 

[vGoodtimes]

There are rare cases for adding noise other than uniform. I don't know why you want to do this. I suspect you don't know what you are doing but someone told you to do this.

However, you can do this if you want. The general methods are variations on uniform lfsr-based generators and lookup tables. And then various table compression methods and etc...