How to generate FSM for a 3 but parity generator?

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preet

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how to model FSM

i am not able to generate FSM for a three bit parity generator which generate a one if it found odd one's on the three consecutive clocks. can any body help me

i have made the above using shift reg but want to know how to do it using FSM

Regards,
Preet
 

Re: how to model FSM

you dont know the coding style for FSM, or you just need someone to give you the state diagram for this operation?
 

Re: how to model FSM

just wanted to know state diagram
 

Re: how to model FSM

Are you need a VHDL-FSM source?
 

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