Hi, guys, I think you have got confused by the clock in different models.
In ASIC design, there are at least 3 models, one is RTL-Testbench, one is RTL-Syn-STA, and the other is Chip-board. In 1st model, clock is define by the HDL, just as the upper guys defined in VHDL; in 2nd model, clock is generated by the synthesis DC or PrimeTime tools, and the clock, which frequence is defined by DC or PT, is used to calculate the flip-flop path and find out the critical path; and in 3rd model, after tape out, the clock pin in chip are connected to Crystal on the board.
I think these 3 clocks are the same one, just they have different definitions, defiferent meanings and different usages in different design processes and models.
Rgds,
Wayne