How to generate clock

[santuvlsi]

meaning clock your flop

Friends,

How to generate Clock . As for flip flop, clk has to given as input.

From where do we get this clock.

Santu

 

[ankit12345]

Using HDL??

....be clear.

 

[sam536]

your question can be understood in several ways. You should be clear what you need to clarify here.

In your design, clock can be your Primary port or clock can be generated from the internal circuit in the design , which can trigger your synchronus elements like Flops. Hope you are familiar with clock dividers in the design.

The primary clock can be generated through PLL or any other clock generator circuit. It can be simple symmetrical square wave . The basic things required for clock generator are resonant circuit and an amplifier..

let us know if you are expecting some thing else...

Regards,
Sam

 

[avimit]

On physcial chip, it comes as an input, which in turn comes form a crystal oscillator. Inside the chip, it usually goes into a PLL, gets multiplied, and then it may be used down the design, where it may feed your FFs.

in HDL
SIGNAL clk : std_logic := '0';
.
.
.

clk <= not(clk) after 5 ns;
hope it helps,
Kr,
Avi

 

[meetspraveen]

hi

entity dff is
port( d:in std_logic;
clk:in std_logic;
qut std_logic);
end dff;
architecture beh of dff is
begin
process(clk)
if clk'event and clk='1' then
q<=d;
end if;
end process;
end beh;

see clk in this code is forced using modelsim while simulating
while implementing we assign the corresponding clk pin number to your code clk in UCF file.

i hope this has u

 

[santuvlsi]

Hai friends,

Thanks for giving best replies,

Let me get cleared in one more confusion

Writing HDL will generate clock fine, this in front end.

Clock gets generated.

Coming to backend how this generated clock comes into picture?

After synthesis we get a netlist . do this netlist includes the hardware of clock?

Then we design a IC where clock has to be given as input, normally oscillator are used.(We say for a microprocessor connect 32.5Mhz clock to the clock input PINs)

Now what is use of the clock we generated using HDL and what is the use of Oscillator clock.

I am unbale to understand the difference

 

[pintuinvlsi]

In SOC clocks are generated from PLL. PLLs are supplied a low reference frequency.

 

[WzWzWz]

I try to ask your question.
From digital view. all the generated clocks are from a standard external Oscillator or Crystal, chip RTL and synthesis only generated different frequency clocks for internal usage based on this standard clock.
BTW, you can use other ways to generate clock without source.

 

[mta97e]

Now what is use of the clock we generated using HDL and what is the use of Oscillator clock.

I think you are confused. Clock generated in HDL are just for test purpose. They are not the part of silicon.

 

[rsrinivas]

Now what is use of the clock we generated using HDL and what is the use of Oscillator clock.

I think you are confused. Clock generated in HDL are just for test purpose. They are not the part of silicon.

agree.

 

[vlsichipdesigner]

Dear designer,

my 2 cents in this discussion...

RTL is a way of an abstraction, where when you refer to a clock definition in the sequential block ,means what clock your flop works and what logic you want to capture and all that stuff.

Lets try to understand the concepts
1. The clock is given at the Clock pad, usually a slow frequency clock, due to the limitation of the Pad's and noise issues.
2. The clock is inputted to the Clock Generation Unit block(usually all most all the Chips have this), this block will have PLL(Phase locked loop), the purpose of this block is to Generate all the clock frequencies.

How did we model...
3. In the stage of RTL you write code in such a way what kind of clock the flop has and what kind of data it has to capture.
4. While performing synthesis you specify all your relevant clock definitions and its clock frequencies and synthesis the logic and guarantee that the design works for the specific frequencies targetted for a targetted process technology (say 130nm/90nm/45nm). The synthesis tool is provided with the library information specific to the technology which is characterized for a specific process.

Explains the Synthesis flow
https://www.vlsichipdesign.com/asicsynthesisflow.html

Explains how to write synthesis Constraints file
https://www.vlsichipdesign.com/synopsys_constraints.html

5. In the stage of Place and Route we build Clock -tree's for these specific clocks and ensure those specific clocks arrive at the same time to all the relevant flops .

6. It is the logic which determines whether the data is valid across clock-clocking interfaces and all that stuff...

Explains the scenario for False/Multi/Source synchronous Paths
https://www.vlsichipdesign.com/static timing analysis.html

hope i did not complicate the problem of your understanding.

Praise the Lord

best regards,
vlsichipdesigner
https://www.vlsichipdesign.com
[Learn ASIC design for free]

 

[waynejwd]

Hi, guys, I think you have got confused by the clock in different models.
In ASIC design, there are at least 3 models, one is RTL-Testbench, one is RTL-Syn-STA, and the other is Chip-board. In 1st model, clock is define by the HDL, just as the upper guys defined in VHDL; in 2nd model, clock is generated by the synthesis DC or PrimeTime tools, and the clock, which frequence is defined by DC or PT, is used to calculate the flip-flop path and find out the critical path; and in 3rd model, after tape out, the clock pin in chip are connected to Crystal on the board.
I think these 3 clocks are the same one, just they have different definitions, defiferent meanings and different usages in different design processes and models.

Rgds,

Wayne

 

[ubna]

Physically ckocks are generated from crystal oscillators...

 

[meetspraveen]

hi santu

modelsim forced CLK is only for simulation(only to check)...this clk will not be used during implementation
for real tim osicilator clk will be used

 

[armardu]

From digital view. all the generated clocks are from a standard external Oscillator or Crystal, chip RTL and synthesis only generated different frequency clocks for internal usage based on this standard clock.
BTW, you can use other ways to generate clock without source.

 

[shiv_emf]

in testbench !
always
#delay a=~a;

hope this helps