Hi Liletian:
I think you know your ADC&DAC timing clearly. Tell your digital engineer the timing spec, you'd better draw a detail timing diagram for digital engineer. I am not digital engineer, I only tell my request to digital engineer in our design team. the timing of digital part generate by digital synthesis.
Added after 7 minutes:
The input of digital block is the PLL's output. I think the digital engineer generate the low speed clock by digital divider.