how to generate a reset internally on spartan-6?

[buenos]

Hi

Is it possible to generate a short reset signal for internal logic without using a reset input pin to the FPGA?

I screwed up the PCB and the reset input is not available, I need to reset the internal logic by using an internally generated reset signal. For example when the FPGA configuration finishes, I need a counter to have a "0000000000000000" value. That counter will generate a 100ms reset for the rest of the logic. A 25MHz input clock is available, but the problem is how to make sure that the counter starts at 0x0000 value after config?
This is in VHDL and xilinx spartan-6 FPGA.

 

[mrflibble]

A global reset is applied after configuration by the GSR circuitry. In your HDL you just have to make sure you set the initial value.

module example;

reg [7:0] counter = 0;  // initial value

// some actual code

endmodule

something like that...

Also, if you don't specify an init value, by default the registers will be initialized to a 0 value.

It is however still useful to provide an initial value, since this also helps prevent surprises during simulation.

 

[lucbra]

Another way is to use the LOCK signal from one of the PLL's. Like this you have a sort of control mechanism that when the PLL is not running, the internal logic is kept in a defined state.

I had the same issue some time ago (fucked up PCB)...

Good luck

 

[buenos]

hi
thanx.

the init value has effect only in simulation.

i think the PLLs are first resetted, then they lock. i will check the clocking datasheet if they can run without a reset.

actually i found a kind of solution:
two 16bit timers without init value count up/down then they release reset1 and reset2 after reaching max/min values (0...2ms depending the starting random value). a third counter (22bit) is initialized to zero by both other counters, and it generates the final system reset. i think i have a 1/2^32 chance that this will not generate a reset pulse, and when it does it should do a 100...102ms reset pulse after powerup.

	--RESET PCB BUG WORKAROUND:-------------------------------------------------------------
	--On board-revision-1 there is a bug that makes the PCIe card-edge reset to be unusable.
	--As a workaround, generate a reset internally:
	--the counter is 22-bit, and generates a 100ms reset
	sys_reset_n <= sys_reset_n_local;
 process ( sys_reset_n_local_2ms, sys_reset_n_local_2msb, x25m_clkin)
    begin
       if (sys_reset_n_local_2ms='0' or sys_reset_n_local_2msb='0') then
			sysreset_counter <= (others => '0');
			sys_reset_n_local <= '0';
		 elsif (x25m_clkin'event and x25m_clkin='0') then --falling edge deassertion for good rec/rem timing
			if (sysreset_counter = "1001100010010110100000") then 
			  sys_reset_n_local <= '1';
			  --stop counting
			else
			  sysreset_counter <= sysreset_counter +1;
			  sys_reset_n_local <= '0';
			end if;
       end if;
    end process;	
	 --This is to generate a reset signal for the reset generator:
	 --Unfortunatelly the counter starts at a random number, so the reset delay can be anywhere between 0ms...2ms.
	 --The counter is doubled, one counts up the other one down. so if all bits start at 0000 or at 1111 the first 
	 --stage should still generate a few clock cycles reset to the main reset counter above.
 process ( x25m_clkin)
    begin
       if (x25m_clkin'event and x25m_clkin='1') then
			if (sysreset_counter_2ms = "1111111100000000") then --2ms if it started from zero
			  sys_reset_n_local_2ms <= '1';
			  --stop counting
			else
			  sysreset_counter_2ms <= sysreset_counter_2ms +1;
			  sys_reset_n_local_2ms <= '0';
			end if;
			if (sysreset_counter_2msb = "0000000000000000") then --2ms if it started from oxFFFF
			  sys_reset_n_local_2msb <= '1';
			  --stop counting
			else
			  sysreset_counter_2msb <= sysreset_counter_2msb -1;
			  sys_reset_n_local_2msb <= '0';
			end if;
       end if;
    end process;

 

[mrflibble]

the init value has effect only in simulation.

Nope. For xst of a recent ISE version it picks up the initialization values as well. You can verify this by doing a "view technology schematic", and seeing a flip-flop gets a post-config set or reset. Or check it in fpga editor...

 

[buenos]

"seeing a flip-flop gets a post-config set or reset"
is there a way to instantiate this manually? (other than using an init value)
is it working in both verilog and VHDL?
I like to use universal coding techniques that works on every FPGA and every tool version, this ise version dependency would not be like that, and it would not be fully under my control.

 

[mrflibble]

Instantiate this manually? Instantiate a flip-flop primitive. But that would be vendor specific.

Another reason I like to use the init values is that way (using the GSR) is that this doesn't take up any routing resources. Which the roll-your-own reset signal definitely does. But that's a tradeoff I suppose...