Re: How to generate a power on reset (POR) using digital logic only ? (not through po
I doubt this is practical as a true "logic only" (std
cell CMOS gates or CLBs) design unless you are given
some (dependable) resource besides the supply. You
might be able to make a "foot race" supply voltage
detector using skewed-strength inverters. But in my
work it's always been "analog-y" due to a need to
hold up over wide ranges of supply dV/dt, have a
hysteresis to prevent "chatter", have no weird
misbehaviors below trip level and so on.
If you are allowed to use resistors, capacitors
and loose FETs you have a lot more design latitude
(and probability of success).