use vhdl/verilog language templates in your system. For a example Xilinx ISE has a good set of hdl synthesis templates(counters, block ram, ...). if you know a little of verilog i will understande.
Block Dual RAM :
parameter RAM_WIDTH = <ram_width>;
parameter RAM_ADDR_BITS = <ram_addr_bits>;
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
reg [RAM_WIDTH-1:0] <output_data>;
<reg_or_wire> [RAM_ADDR_BITS-1:0] <read_address>, <write_address>;
<reg_or_wire> [RAM_WIDTH-1:0] <input_data>;
// The following code is only necessary if you wish to initialize the RAM
// contents via an external file (use $readmemb for binary data)
initial
$readmemh("<data_file_name>", <rom_name>, <begin_address>, <end_address>);
always @(posedge <clock>) begin
if (<write_enable>)
<ram_name>[<write_address>] <= <input_data>;
<output_data> <= <ram_name>[<read_address>];
end
---------- Post added at 16:35 ---------- Previous post was at 16:34 ----------
Pardon , "if you know a little of verilog i will understande" -> if you know a little of verilog YOU will understand )