How to generate a checker for fifo

[sai685]

I have a code of testbench for fifo in the below. please tell me how to generate a checker \

• wr_full is asserted when the fifo has 32 element.
• rd_empty is asserted when the fifo has 0 element.

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Code Verilog - [expand]
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module fifo_top_tb;
  reg wr_clk,rd_clk;
  reg[31:0] data_in;
  wire[31:0] data_out;
  wire rd_empty,wr_full;
  reg reset_w;
  reg reset_r;
  reg write_enable,read_enable;
  reg rptr,wptr;
  bit [:0] que [$]; 
  
  fifo_top top1(.wdata(data_in),
    .rdata(data_out),
    .wclk(wr_clk),
    .rclk(rd_clk),
    .wreset_b(reset_w),
    .rreset_b(reset_r),
    .write(write_enable),
    .read(read_enable),
    .rempty(rd_empty),
    .wfull(wr_full));
 
  task reset;
    write_enable =0;
    read_enable =0; 
    wr_clk=0;
    rd_clk=0;
    data_in=0;
    reset_w=0;
    reset_r=0;           // asserted
  endtask
 
  task write; //TODO: random, value (input );
    @(posedge wr_clk)
      begin
      data_in =$random;
      write_enable=1;
      if(!wr_full)
      begin  
          que.push_back(data_in);
 $display ("%t - queue write data = %d", $time, data_in);
 $display("que.size=%d",que.size);
      end
      end
    endtask 
    always
        #5 wr_clk= ~wr_clk;
 
    always @(posedge wr_clk or posedge rd_clk)
      begin
        if(que.size==1)
      begin
         $display("empty");
      end
        else if(que.size==32)
      begin
         $display("full");
      end 
      end
      
  task read; //TODO: random, value ;
      @(posedge rd_clk)
      begin
      read_enable=1;
      if(!rd_empty)
      begin
      que.pop_front();
   $display (" queue data = %d", que.pop_front() );
   $display("que.size=%d",que.size); 
      end
      end
      endtask
      always
        #5 rd_clk=~rd_clk;
     
  initial
  begin
      reset;
      #20 reset_w =~reset_w;
      #20 reset_r =~reset_r;
 
    repeat(32)write;
    fork
    
     read;
     write;   
   join
 
  end
 
  //C H E C K E R
  
  initial
  fork                  
     assert (wr_full==que[32])
     else
     $error("it is wrong");
     assert (rd_empty==que[0])
     else
     $error("it is wrong");
  join
 
  
  
  initial   
                                      $monitor("wr_clk=%d,reset_w=%d,reset_r=%d,write_enable=%d,read_enable=%d,data_in=%d,data_out=%d,wr_full=%d,rd_empty=%d",wr_clk,reset_w,reset_r,write_enable,read_enable,data_in,data_out,wr_full,rd_empty);
 
  initial  #1200 $finish;
    
  initial
  
  begin
   
$dumpfile("fifo_top_tb.vcd");
 $dumpvars(wr_clk,reset_w,reset_r,write_enable,read_enable,data_in,data_out,wr_full,rd_empty);
 
  end
 
   
endmodule

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